JPH04111284A - Information recording and reproducing device - Google Patents

Abstract

PURPOSE:To surely detect a sector address when data is reproduced by outputting information preserved in a register by incrementing when no sector address detection signal is outputted. CONSTITUTION:A detection pulse P1 outputted from a sector mark detection circuit 2 is added on an address mark detection circuit 3 and an address mark detection interpolation circuit 11. In such a case, sector address information preserved in the register 19 is incremented and is outputted as the sector address information of a sector when no sector address detection signal is outputted from a sector address detection circuit. An incrmentor 18 is the one to increase the value of input data by one when the output signal of an OR circuit 17 is added on a clock input terminal CK, and the output data of the circuit is added on the input terminal of the register 19. Thereby, it is possible to surely detect the sector address even when a data error occurs frequently.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention records/reproduces data in units of sectors of a predetermined data length, and also provides sector address information and sector information for identifying sectors immediately before a data area. The present invention relates to an information recording/reproducing apparatus that records/reproduces data on a storage medium having a data format to which a sector synchronization signal for detecting address information is added.

[Prior Art] For example, in a write-once optical disk device, data is recorded/reproduced in sector units of a predetermined data length, and sector address information and sector address information for identifying the sector are detected immediately before the data area. Data is recorded/reproduced on a storage medium that has a data format to which a sector synchronization signal is added for data storage.
Shown in Figure (a).

The sector areas that make up one sector include a preamble area where sector addresses are recorded to identify each sector, a flag area where the usage status of the sector is recorded, and data where user data is recorded. and a buffer area forming a compensation interval to the next sector.

As shown in FIG. 5B, at the beginning of the preamble area, there is a sector mark SM for identifying the beginning of the sector area.
Following this sector mark SM, a synchronization signal for synchronizing the timing of the signal reproduction system, a sector address SAt! :Address mark A for m punishment
Three identification parts consisting of M and sector address SA are repeatedly arranged.

As shown in FIG. 3(c), the sector address SA includes a track number for identifying the recording track in which the sector is included, a sector number for identifying the sector position within the recording track, and a track number. Cyclic redundancy check code CRC for detecting sector number errors
Consisting of

Here, data is recorded in the sector address SA according to the same modulation rule as the data area, and the sector mark SM and address mark AM are set to data patterns that deviate from this modulation rule.

Furthermore, a longer data pattern is used for the sector mark SH so that the i-word reproduction system can reliably detect it.

FIG. 4 shows a conventional example of a signal reproducing system.

A reproduced signal RF obtained by an optical pickup device (not shown) reproduces data recorded on a write-once optical disc is transmitted to a demodulator 1.
, sector mark detection circuit 2 for detecting sector mark SM, and address mark detection circuit 3 for detecting address mark AM.

The demodulator 1 forms reproduced data DR by applying a predetermined demodulation rule to the reproduced signal RF, and the reproduced data OR is applied to a sector address detection circuit 4 for detecting a sector address SA. , are output to the next-stage control device (not shown).

The sector mark detection circuit 2 compares whether the input reproduction signal RF matches the reproduction signal of the data pattern set in the sector mark SH and
M is detected, and when sector mark SM is detected, a detection pulse P1 is output. Further, when the sector mark detection circuit 2 fails to detect the sector mark SM after a period corresponding to the detection timing of the sector mark SM of the next sector has elapsed after detecting the sector mark SM of the immediately previous sector, , an interpolated pulse is formed and output as a detection pulse P1.

This detection pulse P1 is applied to the address mark detection circuit 3.

The address mark detection circuit 3 is the sector mark detection circuit 2.
The operation starts when the detection pulse P1 is applied to the address mark AM, and it compares whether the input reproduction signal RF matches the reproduction signal of the data pattern set in the address mark AM. When address mark AM is detected, detection pulse P2 is outputted and detection signal S1 is raised to logic 1 level. The detection pulse P2 is applied to the sector address detection circuit 4, and the detection signal S1 is applied to one input terminal of the AND circuit 5.

When the detection pulse P2 is applied from the address mark detection circuit 3, the sector address detection circuit 4 cuts out the reproduced data DR inputted from the demodulator 1 by the data length of the sector address SA, performs an error check on the sector address SA, Sector address SA that does not include data errors
If it can be detected, at that point the detection signal S2 is raised to a logic H level, and sector address data DS consisting of a track number and a sector number is output to the next stage device.

The output signal of the AND circuit 5 is output to the next stage control device as a sector address detection signal ST which indicates that the sector address SA has been detected.

Further, the reset signal R5T is output from the next-stage control device at the end timing of one sector area, and is applied to the reset input terminals of the address mark detection circuit 3 and the sector address detection circuit 4, respectively.

With the above configuration, when the reproduction signal RF of one sector is applied as shown in FIG. Since the mark SM is detected,
As shown in FIG. 2B, the sector mark detection circuit 2 outputs a detection pulse P1.

As a result, the address mark detection circuit 3 starts its detection operation, and at the timing when the rear end of the address mark AM is reproduced, the address mark detection circuit 3 enters the detection state of each address mark AM. As shown in (C), the detection pulse P2 is output from the address mark detection circuit 3 according to each detection timing, and the detection signal S] changes to logic I (level) at the detection timing of the first address mark AM. stand up (same figure (d)
)reference).

On the other hand, the sector address detection circuit 4 detects the sector address SA every time the detection pulse P2 is applied, and at the timing when the sector address SA can be detected, raises the detection signal S2 to a logic H level, and also detects the sector address SA. Output data DS.

Therefore, when the sector address detection circuit 4 is able to detect one or more sector addresses SA among the three sector addresses SA arranged in the preamble area,
At the timing when the first sector address SA is detected, the detection signal S2 rises to the logic H level.

On the other hand, the detection operation of the sector address detection circuit 4 is performed on the condition that the address mark detection circuit 3 detects the address mark AM. The detection signal S1 output from the detection circuit 3 has risen to logic 1 (level).

As a result, when the sector address detection circuit 4 detects the first sector address SA and raises the detection signal S2 to the logic H level, the detection signal S1 applied to the AND circuit 5 is already at the logic H level. Since the voltage has risen and the AND circuit 5 is ready for operation,
Sector address detection signal S output from AND circuit 5
T rises to a logic H level, and this state is maintained until a reset signal R3T is output from the control device.

Therefore, by checking the sector address detection signal ST immediately before the data area detection timing, the control device can determine whether the sector address SA has been detected, and the sector address detection signal ST is at a logic high level.
When the level has been raised, the sector address data DS is taken in at that time and the sector address SA of the sector being reproduced is determined.

In this way, if one or more of the three sector addresses SA arranged in the preamble area can be detected, the sector address SA of that sector can be obtained, which reduces the data error rate of the write-once optical disk used as a storage medium. Data recording/reproduction can be performed even if the size is relatively large.

[Problems to be Solved by the Invention] However, such conventional devices have the following disadvantages.

That is, for example, if there are frequent data errors in the preamble area of the target sector and the sector address SA cannot be detected during data recording, replacement sector processing is performed to replace that sector with another sector. Due to a data error that occurred after recording, the sector address SA
If a situation arises in which it cannot be detected, the recorded data cannot be reproduced, which is an inconvenience.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an information recording/reproducing apparatus that can reliably detect sector addresses during data reproduction.

[Means for Solving the Problems] The present invention provides a sector synchronization signal detection circuit that inputs a reproduction signal and detects a sector synchronization signal, a demodulator that inputs the reproduction signal and demodulates the reproduction data, and A sector address detection circuit that detects and extracts sector address information based on output playback data, and a sector synchronization signal detection signal output from the sector synchronization signal detection circuit or a sector address detection signal output from the sector address detection circuit. a gate circuit that outputs the sector address information as an input timing signal for playback data, a register that stores the sector address information output from the sector address detection circuit, and a register that stores the sector address information when the sector address detection circuit does not output the sector address detection signal. The sector address interpolation means is provided for incrementing the sector address information of the sector and outputting the incremented sector address information as the sector address information of the sector.

[Effects] Therefore, if either the sector synchronization signal or the sector address can be detected, that sector is determined to be a normal sector, and if the sector address cannot be detected, the most recently detected sector address is determined. Since sector addresses that cannot be detected are interpolated based on the data, sector addresses can be detected more reliably even when data errors occur frequently.

[Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows a signal reproducing system according to an embodiment of the present invention. In this figure, the same parts and corresponding parts as in FIG. 4 are given the same reference numerals.

In the figure, a detection pulse P1 output from a sector mark detection circuit 2 is applied to an address mark detection circuit 3 and an address mark detection interpolation circuit 11. Also, the detection signal S output from the address mark detection circuit 3
1 is one input terminal of the AND circuit 5 and the OR circuit 12
is applied to one input end of the .

When the address mark detection interpolation circuit 111 outputs the detection pulse P2 from the address mark detection circuit 3, the address mark detection interpolation circuit 111 outputs the detection interpolation pulse P2a and also outputs the address mark AM
When the detection pulse P2 is not output at the expected detection timing, a complementary pulse that complements the detected pulse P2 is internally formed and output as a detected complementary pulse P2a.

That is, the detection pulse P1 from the sector mark detection circuit 2
After the clock signal CP is outputted, the counted value of the clock signal CP outputted from the clock generation circuit 13 becomes the sector mark SM.
When the value corresponding to the period from detection of address mark AM to detection of the first address mark AM is reached, and after the detection pulse P2 output from the address mark detection circuit 3 is output, the next address mark static When the detection pulse P2 reaches a value corresponding to the period until detection, if the detection pulse P2 is not output at that timing, a complementary pulse is internally formed and output as the detected complementary pulse Pea.

This detected complementary pulse P2a is output to the sector address detection circuit 14.

When the sector address detection circuit 14 receives the detection complement pulse P2a from the address mark detection complement circuit 11,
The reproduced data DR input from the demodulator 1 is cut out by the data length of the sector address SA, and an error check is performed on the sector address SA. When the error check is completed three times corresponding to one preamble area, a data error is detected. If one or more sector addresses SA that do not include a
Output. Further, if the sector address SA cannot be detected after completing the error check three times corresponding to one preamble area, a non-detection pulse P4 is output.

The detection signal S2a is applied to the other input terminal of the AND circuit 5 and the other input terminal of the OR circuit 12, and the sector address data DSa is applied to one input terminal A of the comparator 15, and the data of the counter 16 It is added to the input end. Further, the detection pulse P3 is applied to the load input terminal LD of the counter 16 and is applied to one input terminal of the OR circuit 17, and the non-detection pulse P4 is applied to the clock input terminal CK of the counter 16 and is applied to the OR circuit 17. It is applied to the other input terminal of the circuit 17.

When the detection pulse P3 is applied to the load input terminal LD, the counter 16 inputs (loads) the sector address data DSa applied to the data input terminal at that time as a count value, and also inputs (loads) the sector address data DSa applied to the data input terminal at that time as a count value, and also inputs (loads) the sector address data DSa applied to the data input terminal at that time, and also inputs (loads) the sector address data DSa that is applied to the data input terminal at that time, and also inputs (loads) the sector address data DSa that is applied to the data input terminal at that time. When pulse P4 is applied, the held count value is increased by one. The count value of this counter 16 is 1. Incrementer 1
8 and the sector address data Its
The signal is output to the next stage control device (not shown) as a signal.

The incrementer 18 increases the value of input data by one when the output signal of the OR circuit 17 is applied to its clock input terminal CK, and the output data is stored in the register 1.
It is added to the input end of 9.

The register 19 holds the input output data of the incrementer 18 when the detection pulse P1 output from the sector mark detection circuit 2 is applied, and the held data is input to the other input of the comparator 15. It is added to end B.

The comparator 15 compares whether the sector address data DSa applied to the input terminal A and the output data of the register 19 applied to the input terminal B are equal. , which raises the output signal to the logical 1 level, and the output signal is the match signal EQ
It is added to the next stage control device as a.

In addition, the reset signal R3T output from the control device is
It is applied to the reset input terminals R of the address mark detection circuit 3 and the sector address detection circuit 14.

With the above configuration, when the reproduction signal RF of the sector whose sector address SA is n (see FIG. 2(a)) is applied, the sector mark detection circuit 2 detects the sector mark at the timing when the rear end of the sector mark SM is reproduced. Since the mark S is in the detection state, the sector mark detection circuit 2 outputs the detection pulse P1 (
(see FIG. 2(b)) is output.

As a result, the address mark detection circuit 3 and the address mark detection complement circuit 11 start their operations, and at the timing when the rear end of the address mark AM is reproduced, the address mark detection circuit 3 changes to the detection state of each address mark AM. Therefore, the address mark detection circuit 3 outputs the detection pulse P2 (second pulse) according to each detection timing.
(see figure (c)) is output, and the detection signal S1 is set to a logic high level at the detection timing of the first address mark AM.
rising to the level (see Figure 2 (e)), AND circuit 5
becomes operable, and the reproduction address detection signal STr output from the OR circuit 12 rises to the logic H level (see FIG. 2(0)).

As a result, from the address mark detection complement circuit 11,
At the output timing of detection pulse P2, detection complementary pulse P
2a (see FIG. 2(f)) is output.

On the other hand, the sector address detection circuit 4 detects the detected complementary pulse P
The detection operation of the sector address SA is performed every time 2a is added, and if one or more sector addresses SA have been detected when the three detection operations are completed, the detection signal 52a is
(see Fig. 2 (g)) is raised to logic I (level), and a detection pulse P3 (see Fig. 2 (i)) is output.
Output sector address data DSa. in this case,
The non-detection pulse P4 (see FIG. 2(j)) is not output.

As a result, the sector address data DSa is held in the counter 16, and the output data of the counter 16 is output as the sector address data DS (see FIG. 2(h)).

At the same time, the incrementer 18 holds a value (n+1) obtained by adding 1 to the output data of the counter 16, and the value (n+1) is added to the register 19.

Further, the recording sector address detection signal STtg (see FIG. 2(n)) output from the AND circuit 5 is a logic 1.
Rubel stands up.

In this way, the sector address detection circuit 14 detects the three sector addresses S arranged in the preamble area.
When one or more sector addresses SA among A can be detected, when three detection operations are completed, the detection signal S2 is
a rises to the logic H level, and the sector address data DSa detected at that time is output.

This sector address data DSa is held in the counter 16, and the sector address data DSa is held by the counter 16.
Output as S.

Therefore, during data recording, when the recording sector address detection signal STv rises to the logic H level at the timing immediately before the data area, and
During data reproduction, the sector address SA of the sector being accessed is obtained by taking in the sector address data DS when the sector address detection signal STr during reproduction rises to the logic H level at the timing immediately before the data area. be able to.

This state is reset when the reset signal R3T (see FIG. 2(d)) is output from the control device at the end timing of the data area.

Then, when the reproduction signal RF of the sector whose sector address SA is (n+1) is added and the sector mark detection circuit 2 enters the sector mark SM detection state in the same way as described above, the sector mark detection circuit 2 A detection pulse P1 is output.

At this time, the register 19 holds the value (n+1) (see FIG. 2(k)) output from the incrementer 18, and the output data changes to the value (n+]) (see FIG. 2(k)). )reference).

Then, in the same manner as described above, the sector address detection circuit 1
4 detects one or more sector addresses SA and sets the value (n
+1) sector address data DSa, at that point the input values at input terminals A and B of the comparator 15 become equal. ) is output.

Thereby, the control device can determine that consecutive sectors SA are being accessed by monitoring the coincidence signal EQ.

Here, for example, if a data error has occurred in the sector mark SM, the sector mark detection circuit 2
If M cannot be detected, the sector mark detection circuit 2 outputs the detection pulse Pl at the expected timing from the detection timing of the sector mark SH of the immediately preceding sector. The detection circuit 3 and the address mark detection complement circuit 11 can operate.

Further, if a data error occurs in the address mark AM and the address mark detection circuit 3 cannot detect the address mark AM, the address mark detection complement circuit 11
generates a complementary pulse at the expected detection timing of the address mark AM and outputs it as the detected complementary pulse P2a, so the sector address detection circuit 14 can operate in the same manner as described above.

However, in this case, if the address mark detection circuit 3 cannot detect all three address marks AM in the preamble area, the detection signal S1 will not be output from the address mark detection circuit 3. Since the sector address detection signal STV does not rise to the logic H level during recording, the sector address detection state does not occur.

In that case, the control device performs a predetermined sector replacement process and records the data to be recorded in that sector in the alternative sector.

Further, when the sector address detection circuit 14 cannot detect all three sector addresses SA in the preamble area, the sector address detection circuit 14 does not output the sector address data DSa, and in this case, the sector address data DSa is not output. A detection pulse P4 is output.

Therefore, since the counter 16 increases the count value by one,
A value obtained by incrementing the previous sector address SA by one, that is, an expected value of the sector address SA of the currently accessed sector, is output as sector address data DS.

The suitability of this predicted value is determined by the sector address SA of the next sector.
This can be determined by checking the logic level of the match signal EQ output from the comparator circuit 15 at the timing when the sector address data DSa is output from the sector address detection circuit 14 upon detection of the sector address data DSa.

That is, when accessing data in consecutive sectors, it can be determined that the sector address data DS is correct by confirming that the match signal EQ rises to the logic H level corresponding to each sector. .

Furthermore, even if the sector address SA cannot be detected, if the address mark detection circuit 3 detects one or more address marks A, the sector address detection signal ST during reproduction is
Since r rises to a logic H level, the control device can input sector address data DS to identify the sector being accessed.

Note that even in this state, it can be confirmed whether the sector address data DS is correct by the method described above.

In this way, in this embodiment, if the address mark is blank or the sector address SA can be detected, the sector address data DS can be obtained during data reproduction, so the reliability of detecting the sector address SA during data reproduction is improved. .

Therefore, even if a data error occurs after data recording, the probability of detecting the sector address SA is improved, and a reproducing apparatus that is resistant to data errors can be constructed.

In the above-described embodiment, the present invention is applied to a signal reproducing system of a write-once optical disc, but the present invention can be similarly applied to other information recording/reproducing apparatuses.

Furthermore, the present invention can be similarly applied to information recording and reproducing apparatuses that use storage media in data formats other than those of the embodiments described above.

[Effects of the Invention] As explained above, according to the present invention, there are provided a sector synchronization signal detection circuit that inputs a reproduction signal and detects a sector synchronization signal, and a demodulator that inputs a reproduction signal and demodulates reproduction data. , a sector address detection circuit that detects and extracts sector address information based on reproduced data output from the demodulator, and a sector synchronization signal detection signal output from the sector synchronization signal detection circuit or output from the sector address detection circuit. A gate circuit that outputs a sector address detection signal as an input timing signal for reproduced data, a register that stores sector address information output from the sector address detection circuit, and a register that stores sector address information output from the sector address detection circuit, and Equipped with sector address interpolation means that increments the sector address information stored in the register and outputs it as sector address information of the sector, and when either the sector synchronization signal or the sector address can be detected, the sector is classified as a normal sector. In addition, if a sector address cannot be detected, the undetected sector address is interpolated based on the sector address detected immediately before, so even if data errors occur frequently, To obtain the effect that sector addresses can be detected more reliably.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a signal reproducing system according to an embodiment of the present invention, FIG. 2 is an operational waveform diagram for explaining the operation of the device shown in FIG. 1, and FIG. 3(a) is a write-once optical disc. (b) is a schematic diagram illustrating the data format of the preamble area; (C) is a schematic diagram illustrating the data format of the preamble area;
4 is a schematic diagram illustrating the data format of sector addresses.
The figure shows a block diagram of a conventional example of a signal reproducing system, and
FIG. 3 is an operation waveform diagram for explaining the operation of the device shown in the figure. DESCRIPTION OF SYMBOLS 1... Demodulator, 2... Sector mark detection circuit, 3.
... Address mark detection circuit, 11... Address mark detection complement circuit, 12.17... OR circuit, 13...
- Clock generation circuit, 14... Sector address detection circuit, 15... Comparison circuit, 16... Counter, 17.
...Incrementer, 19...Register.

Claims (1)

[Claims] Data is recorded/reproduced in sector units of a predetermined data length, and has a data format in which sector address information for identifying the sector and a sector synchronization signal for detecting the sector address information are added immediately before the data area. An information recording and reproducing device that records/reproduces data on a storage medium includes a sector synchronization signal detection circuit that inputs a reproduction signal and detects a sector synchronization signal, a demodulator that inputs the reproduction signal and demodulates the reproduction data, and a demodulator. a sector address detection circuit that detects and extracts sector address information based on playback data output from the device; and a sector synchronization signal detection signal output from the sector synchronization signal detection circuit or the sector address detection signal output from the sector address detection circuit. a gate circuit that outputs a sector address detection signal as an input timing signal for reproduced data; a register that stores sector address information output from the sector address detection circuit;
The present invention is characterized by comprising sector address interpolation means for incrementing the sector address information stored in the register and outputting the incremented sector address information as sector address information of the sector when the sector address detection signal is not output from the sector address detection circuit. Information recording and reproducing device.