JPH04107949A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH04107949A JPH04107949A JP22738090A JP22738090A JPH04107949A JP H04107949 A JPH04107949 A JP H04107949A JP 22738090 A JP22738090 A JP 22738090A JP 22738090 A JP22738090 A JP 22738090A JP H04107949 A JPH04107949 A JP H04107949A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- width
- groove
- grooves
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000002955 isolation Methods 0.000 claims abstract description 11
- 230000003647 oxidation Effects 0.000 claims abstract description 9
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 5
- 230000007547 defect Effects 0.000 abstract description 11
- 239000013078 crystal Substances 0.000 abstract description 6
- 230000002159 abnormal effect Effects 0.000 abstract description 3
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 238000000926 separation method Methods 0.000 abstract 3
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 239000010410 layer Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Landscapes
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この第1発明は、半導体装置の製造方法、特に素子間分
離方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The first invention relates to a method for manufacturing a semiconductor device, particularly to a method for isolating elements.
この第2の発明は、半導体装置、特に素子間分離された
半導体装置に関するものである。This second invention relates to a semiconductor device, particularly a semiconductor device in which elements are isolated.
半導体集積回路、特にLSIと呼ばれる素子においては
、多くのデバイスか同一の平面に配置されており、相互
干渉による誤動作を避けるために素子と素子の間は電気
的に絶縁されなくてはならない。このいわゆる素子間分
離を行うため、従来よりトレンチアイソレーションと呼
ばれる方法が用いられてきた。In semiconductor integrated circuits, particularly in devices called LSIs, many devices are arranged on the same plane, and the devices must be electrically insulated to avoid malfunctions due to mutual interference. In order to perform this so-called isolation between elements, a method called trench isolation has conventionally been used.
これを図面について説明する。第2図(a)〜(d)は
トレンチアイソレーションの一例を表す断面図であり、
工程順に示したものである。シリコン基板1に不純物を
拡散して埋め込みコレクタ層2を形成した後、エピタキ
シャル成長層3を形成する。次に、エピタキシャル成長
層3上に、第1の酸化膜4を形成する。次に写真製版工
程により第1の酸化膜4をパターニングし、これをマス
クとしてシリコン基板1を、埋め込みコレクタ層2より
深くエツチングして溝5を形成する(第2図(a))。This will be explained with reference to the drawings. FIGS. 2(a) to 2(d) are cross-sectional views showing an example of trench isolation,
The steps are shown in order. After forming a buried collector layer 2 by diffusing impurities into a silicon substrate 1, an epitaxial growth layer 3 is formed. Next, a first oxide film 4 is formed on the epitaxial growth layer 3. Next, the first oxide film 4 is patterned by a photolithography process, and using this as a mask, the silicon substrate 1 is etched deeper than the buried collector layer 2 to form a groove 5 (FIG. 2(a)).
次に溝5の表面に熱酸化により、薄い、例えば溝5の幅
Wの1/10程度の膜厚を有する第2の酸化膜6を形成
する(同図(b))。次にCVD等により埋め込み酸化
膜7を形成して溝5を埋め込む(同図(C))。その後
表面か平らになるように、埋め込み酸化膜7及び第1の
酸化膜4をエッチバックし、その後ベース領域8.エミ
ツタ領域9を、素子形成領域10に形成する(同図(d
))。更に、図示していないが、電極、配線1層間絶縁
膜等を形成して、分離された複数の素子が形成される。Next, a thin second oxide film 6 having a thickness of, for example, about 1/10 of the width W of the groove 5 is formed on the surface of the groove 5 by thermal oxidation (FIG. 5(b)). Next, a buried oxide film 7 is formed by CVD or the like to fill the groove 5 (FIG. 3(C)). Thereafter, the buried oxide film 7 and the first oxide film 4 are etched back so that the surfaces thereof are flat, and then the base region 8. An emitter region 9 is formed in the element formation region 10 ((d) in the same figure).
)). Furthermore, although not shown, electrodes, wiring interlayer insulating films, etc. are formed to form a plurality of separated elements.
従来のトレンチアイソレーションは以上のような工程で
構成されているが、溝5の幅W、隣接する満5の間隔S
、及び第2の酸化膜6を形成する際の酸化温度Tの値に
よっては、応力等のために、埋め込み酸化膜7の形成の
際に素子形成領域10に結晶欠陥が発生する場合があり
、ベース領域8゜エミッタ領域9等で構成されたトラン
ジスタ等が正常に動作しないという問題点があった。Conventional trench isolation consists of the steps described above, but the width W of the groove 5 and the interval S between adjacent grooves 5
, and depending on the value of the oxidation temperature T when forming the second oxide film 6, crystal defects may occur in the element formation region 10 during the formation of the buried oxide film 7 due to stress etc. There is a problem in that a transistor or the like having a base region of 8 degrees and an emitter region of 9 does not operate normally.
この発明は、上記の問題点を解消するためになされもの
で、トレンチアイソレーションにより素子間分離を行っ
ても、結晶欠陥か生じず、トランジスタ等の異常動作を
回避できる半導体装置の製造方法及び半導体装置を得る
ことを目的とする。The present invention was made to solve the above-mentioned problems, and includes a method for manufacturing a semiconductor device and a method for manufacturing a semiconductor device, which does not generate crystal defects even when elements are separated by trench isolation, and can avoid abnormal operation of transistors, etc. The purpose is to obtain equipment.
この第1の発明に係る半導体装置の製造方法では、幅1
μm以下、間隔1μm以上の溝を設け、溝の幅の1/1
0程度の膜厚の熱酸化膜を950℃以下の熱処理で設け
、溝の内部を酸化膜で埋め込むことにより素子間分離を
行うようにしている。In the method for manufacturing a semiconductor device according to the first invention, a width of 1
Provide grooves with an interval of 1 μm or more, and 1/1 of the width of the groove.
A thermal oxide film having a thickness of about 0 is provided by heat treatment at 950° C. or less, and the inside of the trench is filled with the oxide film to provide isolation between elements.
また第2の発明に係る半導体装置は、表面に幅0.6μ
m以下、間隔1μm以上の溝を設け、その内部を酸化膜
で埋め込むようにしている。Further, the semiconductor device according to the second invention has a width of 0.6μ on the surface.
Grooves with an interval of 1 μm or more are provided, and the inside thereof is filled with an oxide film.
溝の幅を1μm以下、間隔を1μm以上とし、この溝に
950℃以下の熱処理によって溝幅の1/10程度の熱
酸化膜を形成し、前記溝の内部を酸化膜で埋め込むこと
で溝周辺の応力を緩和する。The width of the groove is 1 μm or less and the interval is 1 μm or more, and a thermal oxide film of about 1/10 of the groove width is formed in this groove by heat treatment at 950°C or less, and the inside of the groove is filled with the oxide film to improve the periphery of the groove. relieve stress.
又、溝の幅を0.6μm以下、間隔を1μm以上とし、
溝の内部を酸化膜で埋め込むことて溝周辺の応力を緩和
する。In addition, the width of the groove is 0.6 μm or less, the interval is 1 μm or more,
The stress around the trench is alleviated by filling the inside of the trench with an oxide film.
第1図はこの発明の概要を示す、素子形成領域10の欠
陥密度(1μm2当たりの欠陥数)と溝5の幅Wと間隔
Sと第2の熱酸化膜6形成時の酸化温度Tの関係を示し
たクラ7である。図中測定値のバラツキは5′φ基板の
端部と中央部の差異を示している。従来の技術の項で説
明した方法において、満5の幅Wと間隔Sと酸化温度T
を種々選ぶと素子形成領域10に発生する欠陥密度は同
図のように変化するということを発明者は見出した。FIG. 1 shows an overview of the present invention; the relationship among the defect density (number of defects per 1 μm2) in the element formation region 10, the width W and spacing S of the groove 5, and the oxidation temperature T during the formation of the second thermal oxide film 6. This is Kura 7, which showed the following. The variation in the measured values in the figure indicates the difference between the edge and center of the 5'φ substrate. In the method described in the prior art section, the width W, the interval S, and the oxidation temperature T are
The inventor has discovered that when various selections are made, the density of defects occurring in the element forming region 10 changes as shown in the figure.
即ち、溝5の幅Wが1.0μm以下で、隣接する溝5の
間隔Sか1μm以上の溝5を形成した場合において、欠
陥密度をOにするには温度Tを950℃以下にすればよ
いことがわかる。That is, in the case where the width W of the groove 5 is 1.0 μm or less and the interval S between adjacent grooves 5 is 1 μm or more, the temperature T must be set to 950° C. or less in order to reduce the defect density to O. I know it's good.
また、第1図から明らかな様に酸化温度Tが高い場合に
おいて溝5の幅Wが大きくなると、欠陥か増大してゆく
という傾向があるが、WS2.6μmでは酸化温度Tに
依存せず欠陥密度は0となる。即ち、溝5の間隔Sが1
μm以上ある場合に!45の幅Wを0.6μm以下とし
ても同様の効果を奏する。Furthermore, as is clear from FIG. 1, when the oxidation temperature T is high and the width W of the groove 5 increases, there is a tendency for the number of defects to increase. The density becomes 0. That is, the interval S between the grooves 5 is 1
When it is more than μm! The same effect can be obtained even if the width W of 45 is set to 0.6 μm or less.
但し、第2の熱酸化膜6はその厚さを、溝5の幅Wの1
/10程度とする。これよりも厚すぎると溝5の形状か
変形し、またこれよりも薄すぎるとその膜厚が不均一と
なるため、応力か発生するためである。However, the thickness of the second thermal oxide film 6 is 1 of the width W of the groove 5.
/10 or so. This is because if it is too thick, the shape of the groove 5 will be deformed, and if it is too thin, the film thickness will be uneven and stress will occur.
この第1の発明は以上に説明した様に、半導体装置の素
子分離を行う際に、幅1μm以下、間隔1μm以上の溝
を形成し、前記溝の表面に950℃以下の酸化温度で溝
の幅の1/10程度の膜厚の熱酸化膜を形成し、前記溝
の内部を酸化膜で埋め込むので、溝周辺の応力は緩和さ
れ、結晶欠陥の発生を防ぎ、素子の異常動作を回避でき
るという効果がある。As explained above, this first invention forms grooves with a width of 1 μm or less and an interval of 1 μm or more when performing element isolation of a semiconductor device, and oxidizes the surface of the grooves at an oxidation temperature of 950° C. or less. Since a thermal oxide film with a thickness of about 1/10 of the width is formed and the inside of the groove is filled with the oxide film, stress around the groove is relaxed, crystal defects are prevented from occurring, and abnormal operation of the element can be avoided. There is an effect.
この第2の発明は以上に説明した様に、0.6μm以下
の幅を有し、1μm以上の間隔を有する酸化膜で埋め込
まれた複数の溝を表面に備えているので、溝周辺の応力
は緩和され、結晶欠陥の発生を防ぎつつ素子分離できる
という効果がある。As explained above, this second invention has a plurality of grooves on the surface filled with an oxide film having a width of 0.6 μm or less and an interval of 1 μm or more, so that stress around the grooves is reduced. This has the effect of allowing element isolation while preventing crystal defects from occurring.
第1図はこの発明の概要を示すグラフ、第2図(a)〜
(d)はトレンチアイソレーションの工程を工程順に表
わした断面図である。
図において、1は半導体基板、5は溝、6は第2の酸化
膜、Wは溝の幅、Sは溝の間隔、Tは酸化温度である。
なお、各図中同一符号は同一または相当部分を示す。Figure 1 is a graph showing the outline of this invention, Figure 2 (a) -
(d) is a cross-sectional view showing the trench isolation process in order of process. In the figure, 1 is the semiconductor substrate, 5 is the groove, 6 is the second oxide film, W is the width of the groove, S is the interval between the grooves, and T is the oxidation temperature. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (2)
有する半導体装置の製造方法において、半導体基板表面
に幅1μm以下、間隔1μm以上の溝を形成する工程と
、 前記溝の表面に、950℃以下の酸化温度で溝幅の1/
10程度の膜厚の熱酸化膜を形成する工程と、 前記溝の内部を酸化膜で埋め込む工程とを備えたことを
特徴とする半導体装置の製造方法。(1) A method for manufacturing a semiconductor device including an element isolation step of forming grooves on the surface of the semiconductor device, the step of forming grooves with a width of 1 μm or less and an interval of 1 μm or more on the surface of the semiconductor substrate; 1/ of groove width at oxidation temperature below ℃
1. A method for manufacturing a semiconductor device, comprising: forming a thermal oxide film with a thickness of about 10 mm; and burying the inside of the trench with an oxide film.
有する、酸化膜で埋め込まれた複数の溝を表面に備えた
ことを特徴とする半導体装置。(2) A semiconductor device characterized in that its surface is provided with a plurality of grooves filled with an oxide film, each having a width of 0.6 μm or less and an interval of 1 μm or more.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22738090A JPH04107949A (en) | 1990-08-28 | 1990-08-28 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22738090A JPH04107949A (en) | 1990-08-28 | 1990-08-28 | Semiconductor device and its manufacture |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04107949A true JPH04107949A (en) | 1992-04-09 |
Family
ID=16859905
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP22738090A Pending JPH04107949A (en) | 1990-08-28 | 1990-08-28 | Semiconductor device and its manufacture |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04107949A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63258020A (en) * | 1987-04-15 | 1988-10-25 | Nec Corp | Formation of element isolation pattern |
JPH03234042A (en) * | 1990-02-09 | 1991-10-18 | Toshiba Corp | Semiconductor device and its manufacture |
-
1990
- 1990-08-28 JP JP22738090A patent/JPH04107949A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63258020A (en) * | 1987-04-15 | 1988-10-25 | Nec Corp | Formation of element isolation pattern |
JPH03234042A (en) * | 1990-02-09 | 1991-10-18 | Toshiba Corp | Semiconductor device and its manufacture |
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