JPH0410424A - Manufacture of integrated circuit - Google Patents
Manufacture of integrated circuitInfo
- Publication number
- JPH0410424A JPH0410424A JP11193590A JP11193590A JPH0410424A JP H0410424 A JPH0410424 A JP H0410424A JP 11193590 A JP11193590 A JP 11193590A JP 11193590 A JP11193590 A JP 11193590A JP H0410424 A JPH0410424 A JP H0410424A
- Authority
- JP
- Japan
- Prior art keywords
- silicon nitride
- insulating film
- nitride film
- polyimide
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 229920001721 polyimide Polymers 0.000 claims abstract description 51
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 44
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 44
- 239000004642 Polyimide Substances 0.000 claims abstract description 41
- 239000004065 semiconductor Substances 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000001259 photo etching Methods 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 44
- 239000011229 interlayer Substances 0.000 claims description 23
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 230000015556 catabolic process Effects 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 239000007772 electrode material Substances 0.000 claims description 2
- 238000001312 dry etching Methods 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 abstract 1
- 238000012856 packing Methods 0.000 abstract 1
- 239000009719 polyimide resin Substances 0.000 description 10
- 238000002161 passivation Methods 0.000 description 7
- 230000000903 blocking effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 238000000576 coating method Methods 0.000 description 3
- 238000011109 contamination Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は、一つの半導体基板に少なくともＭＩＳ型素子
を集積化した半導体集積回路に関し、特にその多層配線
技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a semiconductor integrated circuit in which at least MIS type elements are integrated on one semiconductor substrate, and particularly to multilayer wiring technology thereof.
（口〉従来の技術
半導体集積回路には、一つの半導体基板にバイポーラト
ランジスタ、ＰチャンネルＭＩ ５ＦＥＴ、Ｎチャンネ
ルＭＩＳＦＥＴの夫々を設けたものがある（例えば、特
開平１−２４５５５３号公報）。(Example) Some conventional semiconductor integrated circuits include a bipolar transistor, a P-channel MI5FET, and an N-channel MISFET on one semiconductor substrate (for example, Japanese Patent Laid-Open No. 1-245553).
このような半導体集積回路の断面図を第３１３０に示す
。同図において、（１）はＰ型半導体基板、（２）は基
板（１）全面に積層して形成したＮ型エピタキシャル層
、（３）は基板（１）表面に形成したＮ１型埋め込み層
、（４）は基板（１）表面に形成したＰ＋型埋め込み層
、（５）はＰ＋型分離領域、及び（６）はフィールド酸
化膜、（７）はＮＰＮトランジスタ（８）のＰ型ベース
領域、（９）は同じ＜ＮＰＮ トランジスタ（８）のＮ
＋型エミッタ領域、（１０）はＮ＋型フレクタコンタク
ト領域、（１１）はＮチャンネル型ＭＯＳトランジスタ
（１２）のＰ型ウェル領域、（１３）はＮチャンネル型
ＭＯＳトランジスタ（１２）のＮ型ソース・ドレイン領
域、（１４）はゲート電極である。尚、Ｐチャンネル型
ＭＯ３）ランジスタは記載していない。（１５）は各素
子の不純物拡散領域にオーミンクコンタクトする第１配
線層、（１６）は層間絶縁膜、（１７）は第２配線層で
ある。A cross-sectional view of such a semiconductor integrated circuit is shown in No. 3130. In the figure, (1) is a P-type semiconductor substrate, (2) is an N-type epitaxial layer formed on the entire surface of the substrate (1), (3) is an N1-type buried layer formed on the surface of the substrate (1), (4) is a P+ type buried layer formed on the surface of the substrate (1), (5) is a P+ type isolation region, (6) is a field oxide film, (7) is a P type base region of an NPN transistor (8), (9) is the same <NPN N of transistor (8)
+ type emitter region, (10) is N+ type flexor contact region, (11) is P type well region of N channel type MOS transistor (12), (13) is N type source of N channel type MOS transistor (12) - Drain region (14) is a gate electrode. Note that the P-channel type MO3) transistor is not shown. (15) is a first wiring layer that makes ohmink contact with the impurity diffusion region of each element, (16) is an interlayer insulating film, and (17) is a second wiring layer.
ＭＯ３型トランジスタを含む半導体集積回路の場合、Ｍ
ＯＳ部のフンタミブロッキング性等の点でパッシベーシ
ョンがシビアになる。その為、従来の層間絶縁膜（１６
）はＰＳＧ等の酸化膜が利用され、最後にＳｉＮ膜でパ
ッシベーションを行なっていた。また、ＰＳＧ等では段
差の平坦化が困難であるので、無機系絶縁膜（ＳＯＧ）
（ｔｇ）による平坦化が行なわれていた。In the case of a semiconductor integrated circuit including an MO3 type transistor, M
Passivation becomes severe in terms of blocking properties of the OS section. Therefore, the conventional interlayer insulating film (16
), an oxide film such as PSG was used, and finally passivation was performed with a SiN film. In addition, since it is difficult to flatten steps with PSG, etc., an inorganic insulating film (SOG) is used.
(tg) flattening was performed.
（ハ）発明が解決しようとする課題
しかしながら、Ｓ ＯＧ （５ｐｉｎ Ｏｎ Ｇｌａｓ
ｓ ） （１８）による平坦化には限度があり、そのた
め工程の複雑化や信頼性の低下を招く欠点があった。(c) Problems to be solved by the invention However, SOG (5pin on glass)
There is a limit to the flattening achieved by (18), which has the disadvantage of complicating the process and reducing reliability.
そこで本願発明者は、層間絶縁膜（１６）として平坦性
に優れ、バイポーラ型ＩＣでの実績が高いポリイミド樹
脂系絶縁膜を用いることを思案した。Therefore, the inventor of the present application considered using a polyimide resin-based insulating film, which has excellent flatness and has a good track record in bipolar ICs, as the interlayer insulating film (16).
ところが、ポリイミド樹脂だけではＭＯＳ部のコンタミ
ブロッキング性に乏しく装置全体の信頼性を損なう欠点
があった。さらに、微細加工に適するポジ型レジストが
ポリイミド系樹脂との選択性の乏しく、これがスルーホ
ールの微細加工を困難にする欠点があった。However, the use of polyimide resin alone has a disadvantage in that the MOS portion has poor contamination blocking properties, impairing the reliability of the entire device. Furthermore, a positive resist suitable for microfabrication has poor selectivity with polyimide resin, which has the disadvantage of making microfabrication of through holes difficult.
（ニ）課題を解決するための手段
本発明は上記従来の欠点に鑑み成きれたもので、眉間絶
縁膜（３７〉をシリコン窒化膜（３９）とポリイミド系
絶縁膜（４０）との積層構造とすることによりＭＯ３素
子に十分なパッシベーション効果を与えると共に、
前記積層層間絶縁膜（３７）にスルーホール（４１）を
開口するに際し、シリコン窒化膜（３９）上に第１のレ
ジストパターン（４３〉を形成する工程と、第１のレジ
ストパターン（４３）をマスクとしてシリコン窒化膜（
３９）を除去する工程と、第１のレジストパターン（４
３）を除去してポリイミド系絶縁膜（４０）を形成する
工程と、ポリイミド系絶縁膜（４０）上に第２のレジス
トパターン（４５）を形成する工程と、第２のレジスト
パターン（４５）をマスクとしてポリイミド系絶縁膜（
４０）を除去する工程とを具備することにより、上記積
層層間絶縁膜（３７）に微細化スルーホール（４１）を
形成できる半導体集積回路の製造方法を提供するもので
ある。(d) Means for Solving the Problems The present invention has been achieved in view of the above-mentioned conventional drawbacks, and the glabella insulating film (37) has a laminated structure of a silicon nitride film (39) and a polyimide insulating film (40). By doing so, a sufficient passivation effect is provided to the MO3 element, and when opening a through hole (41) in the laminated interlayer insulating film (37), a first resist pattern (43) is formed on the silicon nitride film (39). and forming a silicon nitride film (43) using the first resist pattern (43) as a mask.
39) and the step of removing the first resist pattern (4
3) to form a polyimide insulating film (40), a step of forming a second resist pattern (45) on the polyimide insulating film (40), and a step of forming a second resist pattern (45) on the polyimide insulating film (40). Polyimide insulating film (
40), thereby providing a method for manufacturing a semiconductor integrated circuit in which a miniaturized through hole (41) can be formed in the laminated interlayer insulating film (37).
（ホ）作用
本発明によれば、先ずシリコン窒化膜（３９）だけを開
口するので、ポリイミド系絶縁膜（４０）の制限を受け
ずに微細化したスルーホール（４１）の接続部分を形成
できる。その後、ポリイミド系絶縁膜（４０）の形成と
２回目のホトエツチングを行ない、前記シリコン窒化膜
（３９）の開口部よりは大きな開口を形成するが、スル
ーホール（４１）全体としテミレばシリコン窒化膜（３
９）が１回目ホトエツチングにより微細加工されている
ので、微細化されたスルーホール（４１）とすることが
できる。(E) Function According to the present invention, first, only the silicon nitride film (39) is opened, so that the connecting portion of the miniaturized through hole (41) can be formed without being limited by the polyimide insulating film (40). . Thereafter, a polyimide insulating film (40) is formed and a second photo-etching is performed to form an opening larger than the opening in the silicon nitride film (39), but if the through hole (41) is to be formed as a whole, the silicon nitride film will be removed. (3
Since the hole 9) is finely processed by the first photoetching, it is possible to form a fine through hole (41).
また、シリコン窒化膜（３９）が微細化スルーホールを
形成するので、ポリイミド系絶縁膜（４０）の開口は大
きくても高集積化を妨げない。In addition, since the silicon nitride film (39) forms a miniaturized through hole, even if the opening in the polyimide insulating film (40) is large, it does not hinder high integration.
（へ）実施例
以下に本発明の一実施例を図面を参照して詳細に説明す
る。その製造方法を説明するに先立ち、先ず積層構造の
層間絶縁膜を有する半導体集積回路を第２図を用いて説
明する。同図において、（２１）はＰ型シリコン半導体
基板、（２２）は基板（２１）全面にエピタキシャル成
長して形成したＮ−型エピタキシャル層、（２３）はエ
ピタキシヤルＪｉ（２２）を貫通し素子間分離を行なう
Ｐ＋型分離領域、（２４）は分離領域（２３）によって
島状に形成された島領域、（２５）は選択酸化法によっ
て得られたＬＯＧＯ８酸化膜である。（２６）はＮＰＮ
トランジスタ（２７）のＰ型ベース領域、（２８）は
ＮＰＮｈランジスタ（２７）のＮ１型エミッタ領域、（
２９）はＮＰＮ トランジスタ（２７）のＮ＋型フレク
タコンタクト領域、（３０）はＮＰ Ｎ ）−ランジス
タ（２７）の底部に埋め込まれたＮ＋型の埋め込み層で
ある。（３１）はＮｃｈ−ＭＯＳＦＥＴ （３２）のゲ
ート電極、（３３）はＮｃｈ−ＭＯＳＦＥＴ（３２）の
Ｎ＋型ソース・ドレイン電極、（３４）はＮｃｈ−ＭＯ
ＳＦＥＴ（３２）のＰ型ウェル領域、（３５）はＮａｈ
−Ｍ ＯＳ Ｆ Ｅ Ｔ（３２）の底部に埋め込まれ
たＰ＋型の埋め込み層である。尚、図示しないがＰｃｈ
−ＭＯＳＦＥＴはＮ−型エピタキシャル層（２２）の表
面にゲート電極とＰ型ソース・ドレインを設けて形成さ
れる。ゲート電極（３１）は不純物をドープしたポリシ
リコン層から成り、このポリシリコン層はゲート電極（
３１）として用いられる他、ゲート電極（３１）の相互
接続や抵抗素子としても用いられるものである。(F) Example An example of the present invention will be described below in detail with reference to the drawings. Before explaining the manufacturing method thereof, first, a semiconductor integrated circuit having an interlayer insulating film having a stacked structure will be explained with reference to FIG. In the same figure, (21) is a P-type silicon semiconductor substrate, (22) is an N-type epitaxial layer formed by epitaxial growth on the entire surface of the substrate (21), and (23) is an epitaxial layer that penetrates through the epitaxial Ji (22) and is formed between elements. A P+ type isolation region for performing isolation, (24) an island region formed in an island shape by the isolation region (23), and (25) a LOGO8 oxide film obtained by selective oxidation. (26) is NPN
The P-type base region of the transistor (27), (28) the N1-type emitter region of the NPNh transistor (27), (
29) is an N+ type flexor contact region of the NPN transistor (27), and (30) is an N+ type buried layer buried in the bottom of the NPN)-transistor (27). (31) is the gate electrode of Nch-MOSFET (32), (33) is the N+ type source/drain electrode of Nch-MOSFET (32), and (34) is the Nch-MOSFET (32).
P-type well region of SFET (32), (35) is Nah
- This is a P+ type buried layer buried in the bottom of the MOSFET (32). Although not shown, Pch
-MOSFET is formed by providing a gate electrode and a P-type source/drain on the surface of an N--type epitaxial layer (22). The gate electrode (31) consists of a polysilicon layer doped with impurities, and this polysilicon layer serves as the gate electrode (31).
In addition to being used as a gate electrode (31), it is also used as an interconnection of gate electrodes (31) and as a resistance element.
エピタキシャル層（２２）表面に形成きれた個々の素子
は、電極配線によって相互接続され所定の回路機能を構
成する。その電極配線は、先ず各素子の不純物拡散領域
とコンタクトホールを介してオーミンクコンタクトし酸
化膜上を延在する第１配線層（３６）と、第１配線層（
３６）とは層間絶縁膜（３７）によって層間絶縁される
第２配線層（３８）とで形成される。電極材料にはＡｐ
又はＡｊ２−５ｉが用いられる。層間絶縁膜（３７〉は
、第１配線層（３６）やゲート電極（３１）を覆うよう
にプラズマＣＶＤ法によって形成した膜厚数千人のシリ
コン窒化膜（３９）と、シリコン窒化膜（３９）の上に
スピンオン塗布法によって形成した膜厚１，０〜２．０
μのポリイミド系絶縁膜（４０）との２層構成から成る
。第２配線層（３８）はポリイミド系絶縁膜（４０）の
上を延在し、第１配線層（３６）と第２配線層（３８）
とは、層間絶縁膜（３７）に開けられたスルーポール（
４１）を介して層間接続される。スルーホール（４１）
は、ポリイミド系絶縁膜（４０）において側面がテーパ
形状を成して第２配線層（３８）の断線防止とし、シリ
コン窒化膜（３９）においては垂直形成を成して微細コ
ンタクトとする。そして、最終パッシベーション被膜（
４２）には層間絶縁に用いたポリイミド系絶縁膜（４０
）と同系列のポリイミド樹脂をスピンオン塗布して形成
する。The individual elements completely formed on the surface of the epitaxial layer (22) are interconnected by electrode wiring to constitute a predetermined circuit function. The electrode wiring first consists of a first wiring layer (36) that makes ohmink contact with the impurity diffusion region of each element via a contact hole and extends over the oxide film;
36) is formed with a second wiring layer (38) which is interlayer insulated by an interlayer insulating film (37). The electrode material is Ap.
Or Aj2-5i is used. The interlayer insulating film (37) is made of a silicon nitride film (39) with a thickness of several thousand layers formed by the plasma CVD method so as to cover the first wiring layer (36) and the gate electrode (31), and a silicon nitride film (39) that is several thousand thick. ) formed by a spin-on coating method with a film thickness of 1.0 to 2.0
It has a two-layer structure with a polyimide insulating film (40) of μ. The second wiring layer (38) extends over the polyimide insulating film (40), and the first wiring layer (36) and the second wiring layer (38)
is a through pole (
41). Through hole (41)
The polyimide insulating film (40) has a tapered side surface to prevent disconnection of the second wiring layer (38), and the silicon nitride film (39) is vertically formed to form a fine contact. Then, the final passivation film (
42) has a polyimide insulating film (40) used for interlayer insulation.
) is formed by spin-on coating of the same series of polyimide resins.
上記積層した層間絶縁膜（３７）の構成によれば、第１
配線層（３６）やゲート電極（３１）の全面を覆うよう
にシリコン窒化膜（３９）が形成されるので、ＭＯ８素
子のフンタミブロッキング等、素子に対して十分なパッ
シベーション効果を与えることができる。一方、シリコ
ン窒化膜（３９）の上はポリイミド系絶縁膜（４０〉が
スピンオン塗布されて第１配線層（３６）やゲート電極
（３１）が発生する段差を平坦化するので、信頼性の高
い多層配線構造とすることができる。According to the structure of the laminated interlayer insulating film (37), the first
Since the silicon nitride film (39) is formed so as to cover the entire surface of the wiring layer (36) and the gate electrode (31), it is possible to provide a sufficient passivation effect to the device, such as blocking the MO8 device. . On the other hand, a polyimide insulating film (40) is spin-on coated on the silicon nitride film (39) to flatten the step where the first wiring layer (36) and gate electrode (31) occur, making it highly reliable. It can have a multilayer wiring structure.
シリコン窒化膜（３９）の上にポリイミド系絶縁膜（４
０）を形成したのには様々な理由がある。先ず本願と逆
にポリイミド系絶縁膜（４０〉の上にシリコン窒化膜（
３９）を形成した場合は、ポリイミド樹脂によるプラズ
マＣＶＤ装置の汚染の問題が生じる。A polyimide insulating film (4) is formed on the silicon nitride film (39).
0) was formed for various reasons. First, contrary to the present application, a silicon nitride film (
39), there arises a problem of contamination of the plasma CVD apparatus by the polyimide resin.
ＭＯ５型半導体装置では特に良質な膜質が要求されるか
ら、前記製造装置の汚染は当然歩留り低下の要因となる
。さらに、ポリイミド樹脂の全面をシリコン窒化膜（３
９）で覆うと、ポリイミド樹脂が発生するガスの逃げ場
所が無くなってシリコン窒化膜（３９）や第２配線層（
３８）の所謂「ふくれ、が発生し、配線不良となる問題
が生じる。また、第１配線層（３６）の下に形成した場
合は、信頼性の低下を招く。つまり、本願構成の積層構
造とすることが、他の問題を全て解決する手段となるの
である。従って、配線層が３層、４層と増大した場合に
は、２層目と３層目の層間絶縁膜及び３Ｎ１目と４層目
の層間絶縁膜はポリイミド系絶縁膜（４０）のみの単層
構造で行なう。Since particularly good film quality is required for MO5 type semiconductor devices, contamination of the manufacturing equipment naturally causes a decrease in yield. Furthermore, the entire surface of the polyimide resin is coated with a silicon nitride film (3
9), there is no place for the gas generated by the polyimide resin to escape, and the silicon nitride film (39) and the second wiring layer (
38), so-called "bulges" occur, which causes a problem of wiring defects.Furthermore, if it is formed under the first wiring layer (36), reliability will be lowered.In other words, the laminated structure of the present invention This is the means to solve all other problems. Therefore, when the number of wiring layers increases to three or four layers, the interlayer insulating film between the second and third layers and the 3N1 The fourth interlayer insulating film has a single layer structure consisting of only a polyimide insulating film (40).
第１図Ａ乃至第１図Ｆはこのような層間絶縁膜（３７）
にスルーホールを形成できる本願の製造方法を示す断面
図である。Figures 1A to 1F show such interlayer insulating films (37).
FIG. 3 is a cross-sectional view showing the manufacturing method of the present application in which a through hole can be formed in the semiconductor device.
先ず第１図Ａに示す通り、各素子を形成する不純物拡散
領域とゲート電極（３１）の形成が終了したエピタキシ
ャル層（２２）表面の酸化膜を開口してコンタクトホー
ルを形成し、八〇又はＡｊ２−５ｉの蒸着又はスパッタ
による堆積とバターニングにより、各不純物拡散領域に
オーミックコンタクトする第１配線Ｊｌ（３６）を形成
する。そして基板（２１）全面にプラズマＣＶＤ法によ
る膜厚数千人のシリコン窒化膜（３９）を堆積する。シ
リコン窒化膜（３９）自体に平坦化能力のは無いので、
シリコン窒化膜（３９）の表面は第１配線層（３６）や
ゲート電極（３１）の段差がそのまま反映されることに
なる。First, as shown in FIG. 1A, a contact hole is formed by opening the oxide film on the surface of the epitaxial layer (22) on which the impurity diffusion region forming each element and the gate electrode (31) have been formed. By depositing Aj2-5i by evaporation or sputtering and patterning, a first wiring Jl (36) is formed in ohmic contact with each impurity diffusion region. Then, a silicon nitride film (39) with a thickness of several thousand layers is deposited over the entire surface of the substrate (21) by plasma CVD. Since the silicon nitride film (39) itself does not have planarization ability,
The surface of the silicon nitride film (39) directly reflects the steps of the first wiring layer (36) and the gate electrode (31).
次いで第１図Ｂに示す通り、シリコン窒化膜（３９）の
上にポジ型レジストを形成し、これを露光・現像するこ
とで第１のレジストパターン（４３）ヲ形成し、フッ素
系（ＣＨＦ、等）のＲＩＥ（リアクティブ・イオン・エ
ツチング）によってシリコン窒化膜（３９）を異方エツ
チングする。ポジ型レジストはネガ型に比べ微細パター
ンが形成でき、異方エツチングは側壁が垂直となるので
、シリコン窒化膜（３９）の開口部（４４）は微細パタ
ーンとすることができる。Next, as shown in FIG. 1B, a positive resist is formed on the silicon nitride film (39), and this is exposed and developed to form a first resist pattern (43). The silicon nitride film (39) is anisotropically etched by RIE (reactive ion etching). A positive type resist can form a finer pattern than a negative type, and anisotropic etching has vertical sidewalls, so the opening (44) in the silicon nitride film (39) can be formed into a fine pattern.
次いで第１図Ｃに示す通り、第１のレジストパターン（
４３）を除去してポリイミド樹脂をスピンオン塗布し、
ポリイミド系絶縁膜（４０）を形成する。Next, as shown in FIG. 1C, a first resist pattern (
43) was removed and polyimide resin was spin-on applied.
A polyimide insulating film (40) is formed.
膜厚は１．０〜２．０μとし、塗布後は数百℃、数十分
のハードベークを行なう。The film thickness is 1.0 to 2.0 μm, and after coating, hard baking is performed at several hundred degrees Celsius for several tens of minutes.
次いで第１図りに示す通り、ポリイミド系絶縁膜（４０
）の上に今度はネガ型レジストを形成し、これを露光・
現像することで第２のレジストパターン（４５）を形成
し、第２のレジストパターン（４５）をマスクとしてヒ
ドラジン溶液によるウェットエツチングでポリイミド系
絶縁膜（４０）をバターニングする。ネガ型レジストは
前記ヒドラジン溶液に対して耐性を示すので、ポリイミ
ド系絶縁膜（４０）のバターニングマスクとなり得る。Next, as shown in the first diagram, a polyimide insulating film (40
) and then form a negative resist, which is then exposed to light.
A second resist pattern (45) is formed by development, and the polyimide insulating film (40) is patterned by wet etching with a hydrazine solution using the second resist pattern (45) as a mask. Since the negative resist exhibits resistance to the hydrazine solution, it can serve as a patterning mask for the polyimide insulating film (40).
ポジ型レジストでは前記ヒドラジン溶液に溶解してしま
うので、ポジ型レジストを用いることはプロセス的に別
の工夫が必要となる。また、ネガ型レジストはポジ型に
比べて微細加工が出来ないので、その開口は前の工程で
形成したシリコン窒化膜（３９）のものより大きい。第
２のレジストパターン（４５）の開口は第１のレジスト
パターン（４３）の開口と同−軌軸上に形成するだけで
ある０本実施例では、第１のレジストパターン（４３）
の開口に対し、第２のレジストパターン（４５）の開口
は１辺が倍の大きさの正方形で形成した。その結果スル
ーホール（４１）の形状は、ポリイミド系絶縁膜（４０
）で前記ウェットエツチングによりテーバ形状を成し、
シリコン窒化膜（３９）で異方エツチングによる垂直形
状を成し、その底部に１回目ホトエツチングによる微細
加工さレタシリコン窒化膜（３９）の開口がシリコン窒
化膜（３９〉表面の一部を露出するように形成されるこ
とになる。Since a positive resist dissolves in the hydrazine solution, using a positive resist requires a different process. Further, since negative type resists cannot be microfabricated compared to positive type resists, the openings thereof are larger than those of the silicon nitride film (39) formed in the previous step. The openings in the second resist pattern (45) are simply formed on the same axis as the openings in the first resist pattern (43).
The opening of the second resist pattern (45) was formed into a square with one side twice the size of the opening. As a result, the shape of the through hole (41) is similar to that of the polyimide insulating film (40
) to form a Taber shape by the wet etching,
The silicon nitride film (39) is formed into a vertical shape by anisotropic etching, and the bottom of the silicon nitride film (39) is microfabricated by the first photoetching, and the opening in the silicon nitride film (39) exposes a part of the surface of the silicon nitride film (39). It will be formed like this.
尚、ポリイミド系絶縁膜（４０）の開口をシリコン窒化
膜（３９）のものより大きくした結果、２枚のマスクず
れによる他の配線との層間短絡の危惧が生じる。その為
本願は、シリコン窒化膜（３９）の膜厚をその絶縁耐圧
だけで眉間耐圧を満足する厚みとした。このようにして
おけば、近接する他の配線上を覆うポリイミド系絶縁膜
（４０）が全て除去された状態で第２配線層（３８）が
延在しても層間短絡による不良発生は無い。従ってポリ
イミド系絶縁膜（４０）は、絶縁膜としてでは無く単純
に平坦化としての機能を持つことになる。Incidentally, as a result of making the opening of the polyimide insulating film (40) larger than that of the silicon nitride film (39), there is a risk of an interlayer short circuit with other wirings due to misalignment of the two masks. Therefore, in the present application, the thickness of the silicon nitride film (39) is set so that the dielectric breakdown voltage alone satisfies the glabella breakdown voltage. If this is done, even if the second wiring layer (38) extends with the polyimide insulating film (40) covering other adjacent wirings completely removed, no defects will occur due to interlayer short circuits. Therefore, the polyimide insulating film (40) functions not as an insulating film but simply as a flattening film.
次いで第１図Ｅに示す通り、第２のレジストパターン（
４５）を除去した後ポリイミド系絶縁膜（４０〉の表面
に周知の蒸着、又はスパッタ手法によって再度Ａｆｆｉ
又はｋｌ−５ｉを堆積し、これをバターニングすること
により第２配線層（２８〉を形成する。第１配線層（３
６）と第２配線Ｍ （３Ｂ＞とは、微細加工されたシリ
コン窒化膜（３９）の開口を介してコンタクトすること
になる。従って第１配線層（３８）のスルーホールパッ
ドは、ポリイミド系絶縁膜（４０）が大きく開口されて
いても実質的にシリコン窒化膜（３９）の開口に合わせ
て形成すれば良く、配線の高集積化が可能である。Next, as shown in FIG. 1E, a second resist pattern (
After removing the polyimide insulating film (40), Affi is applied again to the surface of the polyimide insulating film (40) using well-known vapor deposition or sputtering techniques.
Alternatively, the second wiring layer (28) is formed by depositing kl-5i and patterning it.The first wiring layer (3
6) and the second wiring M (3B>) will be in contact with each other through an opening in the microfabricated silicon nitride film (39).Thus, the through-hole pad of the first wiring layer (38) is made of polyimide-based Even if the insulating film (40) has a large opening, it can be formed to substantially match the opening of the silicon nitride film (39), and high integration of wiring is possible.
そして第一１図Ｆに示す通り、ポリイミド系樹脂をスピ
ンオン塗布して最終パッシベーション被膜（４２）とし
た。Then, as shown in FIG. 1F, a polyimide resin was spin-on coated to form a final passivation film (42).
このように本願発明の製造方法によれば、シリコン窒化
膜（３９〉だけを先に微細加工を処すので、ポリイミド
を使用した積層構造の層間絶縁膜（３７〉に微細なスル
ーホール（４１〉を形成することができる。As described above, according to the manufacturing method of the present invention, only the silicon nitride film (39) is subjected to microfabrication first, so that fine through holes (41) are formed in the interlayer insulating film (37) of a laminated structure using polyimide. can be formed.
クト）発明の効果
以上に説明した通り、積層構造の層間絶縁膜（３７〉は
、Ｍ２Ｓ部のフンタミブロツキング等パッシベーション
効果を維持しつつ、層間絶縁にポリイミド系絶縁膜（４
０）を利用できる利点を有する。そのため、極めて平坦
な表面を得ることができ、これが信頼性の高い多層配線
構造を提供できる利点を有する他、ポリイミド系絶縁膜
（４０）による平坦化は他のＳＯＧやＰＳＧリフロー等
の平坦化手段よりプロセスが簡単であり、工程の単純化
及びローコスト化が図れる利点を有する。Effects of the Invention As explained above, the interlayer insulating film (37) of the laminated structure maintains the passivation effect such as the blocking of the M2S part, and the polyimide insulating film (47) is used as the interlayer insulation.
0). Therefore, an extremely flat surface can be obtained, which has the advantage of providing a highly reliable multilayer wiring structure, and the polyimide insulating film (40) can be used for flattening using other flattening methods such as SOG or PSG reflow. It has the advantage that the process is simpler and the process can be simplified and costs can be reduced.
モして本発明の製造方法によれば、シリコン窒化膜（３
９）だけを先に微細加工しておくので、ポリイミド樹脂
を使用した層間絶縁膜（３７）に微細な接続開口部を有
するスルーホール（４１）を形成できる利点を有する。Furthermore, according to the manufacturing method of the present invention, a silicon nitride film (3
Since only 9) is microfabricated first, there is an advantage that a through hole (41) having a minute connection opening can be formed in the interlayer insulating film (37) using polyimide resin.
そのため、第１配線層（３６）のスルーホールバッド等
をより微細化し配線密度を向上できる利点を有する。さ
らにシリコン窒化膜（３９〉だけで層間耐圧を満足でき
るようにしておくことにより、第１のレジストパターン
（４３）と第２のレジストパターン（４５）のマスクず
れによる層間短絡の危惧を解消できる利点を有する。そ
して更に、ポリイミド系絶縁膜（４０）は大きな開口面
積を有し且つ側壁がテーバ形状に加工されるので、第２
配線層（３８）の断線、段切れ等の危惧も解消できる利
点を有する。Therefore, there is an advantage that the through-hole pads and the like of the first wiring layer (36) can be further miniaturized and the wiring density can be improved. Furthermore, by making it possible to satisfy the interlayer breakdown voltage with only the silicon nitride film (39), there is an advantage that the fear of interlayer short circuit due to mask misalignment between the first resist pattern (43) and the second resist pattern (45) can be eliminated. Further, since the polyimide insulating film (40) has a large opening area and the side walls are processed into a tapered shape, the second
This has the advantage of eliminating concerns about disconnection, breakage, etc. in the wiring layer (38).
第１図Ａ〜第１図Ｆ及び第２図は本発明を説明する為の
断面図、第３図は従来例を説明する為の断面図である。
２ン1A to 1F and 2 are sectional views for explaining the present invention, and FIG. 3 is a sectional view for explaining a conventional example. 2nd
Claims (6)
積化し、これらを多層配線構造により相互接続した半導
体集積回路の製造方法において、各素子の不純物拡散領
域にコンタクトする第１配線層を形成する工程、 前記第１配線層を覆うようにシリコン窒化膜を形成する
工程、 前記シリコン窒化膜上に第１のレジストパターンを形成
し、前記シリコン窒化膜を異方性エッチングする工程、 前記第１のレジストパターンを除去し、前記シリコン窒
化膜上にポリイミド系絶縁膜を形成する工程、 前記ポリイミド系絶縁膜の上に第２のレジストパターン
を形成し、前記ポリイミド系絶縁膜を等方エッチングす
る工程、 前記レジストパターンを除去し、電極材料の堆積とホト
エッチングによって前記ポリイミド系絶縁膜上を延在し
前記ポリイミド系絶縁膜と前記シリコン窒化膜の開口を
介して前記第１配線層と接続する第２配線層を形成する
工程とを具備することを特徴とする半導体集積回路の製
造方法。(1) In a method for manufacturing a semiconductor integrated circuit in which at least MIS type elements are integrated on the same semiconductor substrate and these elements are interconnected by a multilayer wiring structure, a step of forming a first wiring layer in contact with the impurity diffusion region of each element. , forming a silicon nitride film to cover the first wiring layer; forming a first resist pattern on the silicon nitride film and anisotropically etching the silicon nitride film; a step of removing the pattern and forming a polyimide-based insulating film on the silicon nitride film; a step of forming a second resist pattern on the polyimide-based insulating film and isotropically etching the polyimide-based insulating film; A second wiring is formed by removing the resist pattern and depositing an electrode material and photoetching to extend over the polyimide insulating film and connect to the first wiring layer through openings in the polyimide insulating film and the silicon nitride film. 1. A method for manufacturing a semiconductor integrated circuit, comprising the step of forming a layer.
型素子を共存したものであることを特徴とする請求項第
１項に記載の半導体集積回路の製造方法。(2) The semiconductor integrated circuit is a bipolar type element and an MIS.
2. The method of manufacturing a semiconductor integrated circuit according to claim 1, wherein a mold element is also used.
あり、前記第２のレジストパターンがネガ型レジストで
あることを特徴とする請求項第１項に記載の半導体集積
回路の製造方法。(3) The method for manufacturing a semiconductor integrated circuit according to claim 1, wherein the first resist pattern is a positive type resist, and the second resist pattern is a negative type resist.
記第２配線層との層間絶縁耐圧を満足する厚みであるこ
とを特徴する請求項第１項に記載の半導体集積回路の製
造方法。(4) Manufacturing the semiconductor integrated circuit according to claim 1, wherein the silicon nitride film has a thickness that satisfies an interlayer dielectric breakdown voltage between the first wiring layer and the second wiring layer. Method.
ングであることを特徴とする請求項第１項に記載の半導
体集積回路の製造方法。(5) The method for manufacturing a semiconductor integrated circuit according to claim 1, wherein the etching of the silicon nitride film is dry etching.
ン液によるウェットエッチングであることを特徴とする
請求項第１項に記載の半導体集積回路の製造方法。(6) The method of manufacturing a semiconductor integrated circuit according to claim 1, wherein the polyimide insulating film is etched by wet etching using a hydrazine solution.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2111935A JPH0821583B2 (en) | 1990-04-26 | 1990-04-26 | Method for manufacturing semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2111935A JPH0821583B2 (en) | 1990-04-26 | 1990-04-26 | Method for manufacturing semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0410424A true JPH0410424A (en) | 1992-01-14 |
| JPH0821583B2 JPH0821583B2 (en) | 1996-03-04 |
Family
ID=14573824
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2111935A Expired - Fee Related JPH0821583B2 (en) | 1990-04-26 | 1990-04-26 | Method for manufacturing semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0821583B2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63202939A (en) * | 1987-02-18 | 1988-08-22 | Minolta Camera Co Ltd | Manufacture of multilayer interconnection |
| JPH0228923A (en) * | 1988-07-18 | 1990-01-31 | Sharp Corp | Manufacture of semiconductor device |
-
1990
- 1990-04-26 JP JP2111935A patent/JPH0821583B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63202939A (en) * | 1987-02-18 | 1988-08-22 | Minolta Camera Co Ltd | Manufacture of multilayer interconnection |
| JPH0228923A (en) * | 1988-07-18 | 1990-01-31 | Sharp Corp | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0821583B2 (en) | 1996-03-04 |
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