JPH0399344A - Control storage circuit - Google Patents

Abstract

PURPOSE:To make the reading/writing operation of 1st and 2nd storage circuits each of which is connected to a CPU by one terminal and connected to a logic circuit by the other terminal unrelational to a timing signal outputted from the logic circuit by forcedly outputting a control signal from a CPU to decode the reading/writing operation of the 1st and 2nd storage circuits. CONSTITUTION:The reading/writing operation of the 1st and 2nd storage circuits 4, 5 is controlled by a flip flop (FF) 7 through selection circuits 2, 3. Signals 104, 105 obtained by decoding control signals 102, 107 outputted from the CPU 1 by a control circuit 8 are inputted to the FF 7 to forcedly set/reset the FF 7. Namely when the CPU 1 is driven after starting a system power supply, the output signal 106 of the logic circuit 6 is determined before the arrival of the timing signal 101 of the logic circuit 106 at the FF 7. Thus, the selection circuits 2, 3 controlling the writing/reading of the 1st and 2nd storage circuits 2, 3 can be instantaneously controlled.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control storage circuit that controls a storage circuit connected between a CPU and a logic circuit.

[Conventional technology]

FIG. 4 is a block diagram of an example of a conventional control storage circuit.

In FIG. 4, a control signal from a CPU 30 is written into a memory circuit 32 through a selection circuit 31. Further, the signals read out in time series from the memory circuit 33 are sent to the selection circuit 34.
A time-series control signal is input to the logic circuit 35 through. A selection signal of a selection circuit that controls writing and reading to and from the memory circuits 32 and 33 is output from the flip-flop 36.

[Problem to be solved by the invention]

In the conventional control storage circuit described above, the switching control signal of the storage circuit outputted from the CPU 30 is changed to the output of the flip-flop 36 (the selection circuit 31 .34). Therefore, for example, when the power of the system is turned on, the output of the flip-flop 36 will waste time until the time-series timing signal from the logic circuit 35 is established and reaches the flip-flop 36. It has the disadvantage that initialization cannot be performed quickly.

[Means to solve the problem]

The control storage circuit of the present invention includes first and second storage circuits that alternately store time-series data signals, and a switching circuit that switches between writing and reading out the data signals in the first and second storage circuits. , a flip-flop that controls the switching circuit, and a control circuit that decodes first and second control signals from the CPU and controls the state of the flip-flop.

Further, the control storage circuit of the present invention includes first and second storage circuits that store time-series data signals, an address counter that writes and reads out the data signals to and from the first and second storage circuits, and an address counter that writes and reads the data signals to and from the first and second storage circuits. It has a flip-flop that controls a counter, and control means that decodes first and second control signals from the CPU and controls the state of the flip-flop.

〔Example〕

Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the present invention.

In FIG. 1, a data signal 10B output from the CPUI is written into the first storage circuit 4 by the selection circuit 2. - The signals read out in time series from the memory circuit 5 of the power cylinder 2 are given to the logic circuit 6 through the selection circuit 3.

The selection circuits 2 and 3 for controlling reading and writing of the first and second memory circuits 4 and 5 are controlled by a flip-flop 7. In order to determine the output signal 106 of the flip-flop 7 immediately after the power of the system is turned on, control signals 102 and 107 are output from the CPUI, and the control signals 102 and 107 are decoded by the control circuit 8. Signal 104 decoded by this control circuit 8
．． 105 forcibly sets each flip-flop.

It is given to the flip-flop 7 as a reset signal. That is, when the system power is turned on and the CPUI operates, the output signal 106 of the flip-flop 7 is determined before the timing signal 101 of the logic circuit 6 reaches the flip-flop 7. This makes it possible to immediately control the selection circuit 2.3 which controls the writing and reading of the first and second memory circuits 4.5.

If it is not necessary to quickly control the first and second storage circuits 4.5 as described above, the control signal 1 from the CPU
07 to the flip-flop 7 and after the timing signal 101 from the logic circuit 6 is determined, the output signal 106 of the flip-flop 7 may be determined at a convenient timing.

FIG. 2 is a timing diagram for explaining the operation of the embodiment, and within timings p and q, the timing signal 10
Regardless of the presence or absence of 1, the flip-flop 7
The output signal 106 of will change. Then, within the time period r and s, the control signal 10 from the CPU
2, the signal 106 of the flip-flop 7 is determined when the timing signal 101 from the logic circuit 6 arrives.

In this way, by directly inputting another control line from the CPU 30 to the flip-flops 36 for controlling the selection circuits 31.34, the storage circuits 32. The contents of 33 can be controlled.

FIG. 3 is a block diagram of a second embodiment of the invention. First and second memory circuits 24 that store time-series data signals 203; an address counter 22 that writes and reads data signals 203 and 211 to and from the first and second memory circuits 24 at addresses 204 and 210; counter 22
a flip-flop which is controlled by a timing signal 207, and first and second control signals 201.20 from the CPU 20.
2 and a control means including a decoder 21 for decoding 2 and controlling the state of the flip-flop.

In the third embodiment, the selection circuit 2.3 shown in FIG. 1 is omitted, and the first and second storage circuits 4.5 are represented by 24. However, the operation of the circuit is the same as that of FIGS. 1 and 2. However, in the case of Figure 3, data 20
3 can be written or read, but the data 211
is data read by address 210.

〔Effect of the invention〕

As explained above, the present invention enables read and write operations of the first and second memory circuits, one of which is connected to the CPU and the other to the logic circuit, by outputting a forced control signal from the CPU. By deciphering it, the effect can be achieved regardless of the timing signal from the logic circuit.

[Brief explanation of drawings]

1 and 3 are block diagrams of the first and second embodiments of the present invention, FIG. 2 is a timing diagram for explaining the operation of this embodiment, and FIG. 4 is an example of a conventional control storage circuit. FIG. 1.20...CPU, 2,3...Selection circuit, 4゜5
．． 24...Memory circuit, 6.35...Logic circuit, 7°36...Flip-flop, 8...Control circuit.

Claims (2)

[Claims] (1) A first and a second device that alternately stores time-series data signals.
a storage circuit, a switching circuit for switching between writing and reading out the data signal in the first and second storage circuits, a flip-flop that controls the switching circuit, and a first and second control signal from the CPU. and a control circuit for decoding and controlling the state of the flip-flop. (2) first and second memory circuits that store time-series data signals; an address counter that writes and reads the data signals into and from the first and second memory circuits; and a flip-flop that controls the address counters. , and control means for decoding first and second control signals from a CPU and controlling the state of the flip-flop.