JPH039535U - - Google Patents

Info

Publication number
JPH039535U
JPH039535U JP6884589U JP6884589U JPH039535U JP H039535 U JPH039535 U JP H039535U JP 6884589 U JP6884589 U JP 6884589U JP 6884589 U JP6884589 U JP 6884589U JP H039535 U JPH039535 U JP H039535U
Authority
JP
Japan
Prior art keywords
delay
circuit
cascaded
signal generation
pulse train
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6884589U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP6884589U priority Critical patent/JPH039535U/ja
Publication of JPH039535U publication Critical patent/JPH039535U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Testing Of Individual Semiconductor Devices (AREA)
  • Pulse Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の一実施例を示す接続図、第
2図はこの考案の変形実施例を示す接続図、第3
図は従来の技術を説明するための接続図、第4図
は従来の遅延信号発生回路の動作を説明するため
の波形図、第5図は可変遅延回路の構成を説明す
るための接続図である。 10…第1遅延回路、20…第2遅延回路、1
1A〜11N…縦続接続した遅延素子、12A,
12B,12C…マルチプレクサ。
Fig. 1 is a connection diagram showing one embodiment of this invention, Fig. 2 is a connection diagram showing a modified embodiment of this invention, and Fig. 3 is a connection diagram showing an embodiment of this invention.
The figure is a connection diagram to explain the conventional technology, Figure 4 is a waveform diagram to explain the operation of the conventional delay signal generation circuit, and Figure 5 is a connection diagram to explain the configuration of the variable delay circuit. be. 10...first delay circuit, 20...second delay circuit, 1
1A to 11N...cascaded delay elements, 12A,
12B, 12C...Multiplexer.

Claims (1)

【実用新案登録請求の範囲】 A 一定周期与えられるパルス列の全体に所定の
遅延量を与える第1遅延回路と、上記パルス列を
構成するパルスの相互の時間間隔を制御する第2
遅延回路とを具備した遅延信号発生回路において
、 B 上記第1遅延回路を、複数の遅延素子を縦続
接続した縦接回路と、この縦続接続した遅延素子
の各段間に得られる遅延量の異なる複数の信号の
中の何れか一つを選択して取り出すマルチプレク
サとによつて構成したことを特徴とする遅延信号
発生回路。
[Claims for Utility Model Registration] A. A first delay circuit that provides a predetermined amount of delay to the entire pulse train given at a constant period, and a second delay circuit that controls the mutual time interval of the pulses constituting the pulse train.
B. A delay signal generation circuit comprising a delay circuit, wherein the first delay circuit is a cascaded circuit in which a plurality of delay elements are connected in cascade, and a delay amount obtained between each stage of the cascaded delay elements is different. 1. A delay signal generation circuit comprising a multiplexer that selects and extracts one of a plurality of signals.
JP6884589U 1989-06-12 1989-06-12 Pending JPH039535U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6884589U JPH039535U (en) 1989-06-12 1989-06-12

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6884589U JPH039535U (en) 1989-06-12 1989-06-12

Publications (1)

Publication Number Publication Date
JPH039535U true JPH039535U (en) 1991-01-29

Family

ID=31603632

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6884589U Pending JPH039535U (en) 1989-06-12 1989-06-12

Country Status (1)

Country Link
JP (1) JPH039535U (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58124325A (en) * 1982-01-20 1983-07-23 Hitachi Ltd Shift register with variable number of delay stages
JPS6285514A (en) * 1985-10-11 1987-04-20 Advantest Corp Timing signal generating device
JPS6356827B2 (en) * 1982-09-14 1988-11-09 Trinity Ind Corp
JPS63281268A (en) * 1987-05-14 1988-11-17 Mitsubishi Electric Corp Rotational signal phase-shifting system for rotary device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58124325A (en) * 1982-01-20 1983-07-23 Hitachi Ltd Shift register with variable number of delay stages
JPS6356827B2 (en) * 1982-09-14 1988-11-09 Trinity Ind Corp
JPS6285514A (en) * 1985-10-11 1987-04-20 Advantest Corp Timing signal generating device
JPS63281268A (en) * 1987-05-14 1988-11-17 Mitsubishi Electric Corp Rotational signal phase-shifting system for rotary device

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