JPH0221566U - - Google Patents
Info
- Publication number
- JPH0221566U JPH0221566U JP10044488U JP10044488U JPH0221566U JP H0221566 U JPH0221566 U JP H0221566U JP 10044488 U JP10044488 U JP 10044488U JP 10044488 U JP10044488 U JP 10044488U JP H0221566 U JPH0221566 U JP H0221566U
- Authority
- JP
- Japan
- Prior art keywords
- logic analyzer
- trigger conditions
- acquired
- observe
- waveform
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Tests Of Electronic Circuits (AREA)
Description
第１図は本考案に係る取得データ長可変ロジツ
クアナライザの一実施例を示す構成図、第２図は
タイムチヤートである。
１…入力部、２…リングバツフア、３…メイン
メモリ、４…トリガ条件設定部、５…トリガ回路
、６…第１のメモリ制御回路、７…第２のメモリ
制御回路。
FIG. 1 is a block diagram showing an embodiment of an acquired data length variable logic analyzer according to the present invention, and FIG. 2 is a time chart. DESCRIPTION OF SYMBOLS 1... Input section, 2... Ring buffer, 3... Main memory, 4... Trigger condition setting section, 5... Trigger circuit, 6... First memory control circuit, 7... Second memory control circuit.
Claims (1)
、それをＣＲＴ画面に表示するなどして各信号の
波形を観測あるいは解析することができるように
したロジツクアナライザにおいて、 複数個のトリガ条件を設定し、その複数個のト
リガ条件が満足される期間内のデータのみを取得
できるように構成したことを特徴とする取得デー
タ長可変ロジツクアナライザ。[Scope of Claim for Utility Model Registration] A logic analyzer capable of simultaneously collecting multi-channel digital signals and displaying them on a CRT screen to observe or analyze the waveform of each signal. 1. A logic analyzer with variable acquisition data length, characterized in that it is configured such that trigger conditions can be set and only data within a period in which the plurality of trigger conditions are satisfied can be acquired.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10044488U JPH0221566U (en) | 1988-07-28 | 1988-07-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10044488U JPH0221566U (en) | 1988-07-28 | 1988-07-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0221566U true JPH0221566U (en) | 1990-02-13 |
Family
ID=31328520
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10044488U Pending JPH0221566U (en) | 1988-07-28 | 1988-07-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0221566U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015203701A (en) * | 2014-04-11 | 2015-11-16 | テクトロニクス・インコーポレイテッドＴｅｋｔｒｏｎｉｘ，Ｉｎｃ． | Test and measurement instrument and triggering method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62226064A (en) * | 1986-03-17 | 1987-10-05 | テクトロニツクス・インコ−ポレイテツド | Trigger device |
| JPS62285067A (en) * | 1986-06-03 | 1987-12-10 | Toshiba Corp | Logic analyzer |
| JPS6358265A (en) * | 1986-08-25 | 1988-03-14 | テクトロニックス・インコ−ポレイテッド | Data intake device |
-
1988
- 1988-07-28 JP JP10044488U patent/JPH0221566U/ja active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62226064A (en) * | 1986-03-17 | 1987-10-05 | テクトロニツクス・インコ−ポレイテツド | Trigger device |
| JPS62285067A (en) * | 1986-06-03 | 1987-12-10 | Toshiba Corp | Logic analyzer |
| JPS6358265A (en) * | 1986-08-25 | 1988-03-14 | テクトロニックス・インコ−ポレイテッド | Data intake device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015203701A (en) * | 2014-04-11 | 2015-11-16 | テクトロニクス・インコーポレイテッドＴｅｋｔｒｏｎｉｘ，Ｉｎｃ． | Test and measurement instrument and triggering method |
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