JPH0382069A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPH0382069A JPH0382069A JP1218987A JP21898789A JPH0382069A JP H0382069 A JPH0382069 A JP H0382069A JP 1218987 A JP1218987 A JP 1218987A JP 21898789 A JP21898789 A JP 21898789A JP H0382069 A JPH0382069 A JP H0382069A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- chip
- semiconductor chips
- lead frame
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 6
- 239000010703 silicon Substances 0.000 claims abstract description 6
- 239000002184 metal Substances 0.000 claims abstract description 5
- 229910052751 metal Inorganic materials 0.000 claims abstract description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 8
- 239000011347 resin Substances 0.000 abstract description 7
- 229920005989 resin Polymers 0.000 abstract description 7
- 238000001721 transfer moulding Methods 0.000 abstract description 3
- 238000007789 sealing Methods 0.000 abstract 2
- 230000000694 effects Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、混成集積回路装置の構造に関°する。[Detailed description of the invention] [Industrial application field] The present invention relates to the structure of a hybrid integrated circuit device.
従来、この種の混成集積回路装置には、第３図に示すよ
うに、金属製リードフレーム１上に配線基板２を貼り付
は複数の半導体チップ３．４等を配線基板２上に搭載し
、半導体チップ３．４と配線基板２の間を金線９によっ
てワイヤボンディングし、また、配線基板２とリードフ
レーム１の所定電極の間を金線８によってワイヤボンデ
ィングした後、樹脂１０をトランスファモールド法によ
って封止した構造の混成集積回路装置がある。Conventionally, in this type of hybrid integrated circuit device, as shown in FIG. 3, a wiring board 2 is pasted on a metal lead frame 1, and a plurality of semiconductor chips 3, 4, etc. are mounted on the wiring board 2. After wire bonding is performed between the semiconductor chip 3.4 and the wiring board 2 using a gold wire 9, and wire bonding is performed between the wiring board 2 and a predetermined electrode of the lead frame 1 using a gold wire 8, the resin 10 is transferred and molded. There is a hybrid integrated circuit device having a structure sealed by a method.
上述した、従来の混成集積回路装置は、所定の電気回路
を実現させる手段として、配線基板２上に所定の導体配
線パターンを形成することによっているため、配線密度
は配線基板２のパターン形成上の精度によって決定され
る０通常、配線基板上の最小パターン幅および間隔は各
々例えば、１００μｍ程度となっていた。これは、半導
体チップ３．４内部の配線パターン幅および間隔が２〜
３μｍであるのと比較すると、配線密度が小さく、この
ために、従来の混成集積回路装置の配線密度を大きくで
きないという欠点があった。The above-mentioned conventional hybrid integrated circuit device realizes a predetermined electric circuit by forming a predetermined conductor wiring pattern on the wiring board 2, so the wiring density depends on the pattern formation of the wiring board 2. Normally, the minimum pattern width and interval on a wiring board are each about 100 μm, for example. This means that the wiring pattern width and spacing inside the semiconductor chip 3.4 is
Compared to 3 μm, the wiring density is small, which has the drawback that the wiring density of conventional hybrid integrated circuit devices cannot be increased.
本発明によれば、少なくとも二つの半導体チップと、シ
リコンチップ上に所定の配線を有する配線用チップとを
金属製リードフレーム上にダイボンディングし、半導体
チップ、配線用チップおよびリードフレーム間の所定電
極とを各々ワイヤボンディング法により接続した後樹脂
封止したことを特徴とする混成集積回路装置が得られる
。According to the present invention, at least two semiconductor chips and a wiring chip having predetermined wiring on a silicon chip are die-bonded onto a metal lead frame, and a predetermined electrode is formed between the semiconductor chips, the wiring chip, and the lead frame. A hybrid integrated circuit device is obtained, which is characterized in that the two are connected by a wire bonding method and then sealed with a resin.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の第１の実施例の断面図である。FIG. 1 is a sectional view of a first embodiment of the invention.
リードフレーム１上に、半導体チップ３と半導体チップ
４と、シリコンチップ上に所定の配線を有する配線用チ
ップ５とをダイボンディングし、金線６によって半導体
チップ３．４とリードフレーム１間をワイヤボンディン
グにより接続し、金線７によって半導体チップ３．４と
配線用チップ５とをワイヤボンディングにより接続した
後に、トランスファモールド法により樹脂１０を封止す
る。A semiconductor chip 3, a semiconductor chip 4, and a wiring chip 5 having a predetermined wiring on a silicon chip are die-bonded onto a lead frame 1, and a wire is connected between the semiconductor chip 3.4 and the lead frame 1 using a gold wire 6. After the semiconductor chip 3.4 and the wiring chip 5 are connected by wire bonding using the gold wire 7, the resin 10 is sealed by a transfer molding method.
このように本実施例では、配線基板を用いずに精細な配
線パターンを有する配線用チップを用いているので配線
密度を大きくできる。In this way, in this embodiment, a wiring chip having a fine wiring pattern is used without using a wiring board, so that the wiring density can be increased.
第２図は本発明の第２の実施例の断面図である。リード
フレーム１上に、半導体チップ３．４および配線用チッ
プ５をダイボンディングし、金線７によって各々のチッ
プの所定電極間をワイヤボンディングし、トランスファ
モールド法によってシングルインラインパッケージに樹
脂封止して混成集積回路装置を形成した。FIG. 2 is a sectional view of a second embodiment of the invention. A semiconductor chip 3.4 and a wiring chip 5 are die-bonded onto a lead frame 1, wire-bonded between predetermined electrodes of each chip using a gold wire 7, and resin-sealed into a single in-line package using a transfer molding method. A hybrid integrated circuit device was formed.
以上説明したように本発明は、シリコンウェハー上に精
細な配線パターンを形成した配線用チップを具備してい
るため配線密度を大きくできるという効果がある。As explained above, the present invention has the effect of increasing the wiring density because it includes a wiring chip in which a fine wiring pattern is formed on a silicon wafer.
第１図は本発明の第１の実施例の断面図、第２図は本発
明の第２の実施例の断面図、第３図は従来の混成集積回
路装置の断面図である。
１・・・リードフレーム、２・・・配線基板、３．４・
・・半導体チップ、５・・・配線用チップ、６，７，８
゜９・・・金線、１０・・・樹脂。FIG. 1 is a sectional view of a first embodiment of the invention, FIG. 2 is a sectional view of a second embodiment of the invention, and FIG. 3 is a sectional view of a conventional hybrid integrated circuit device. 1... Lead frame, 2... Wiring board, 3.4.
...Semiconductor chip, 5...Wiring chip, 6, 7, 8
゜9...Gold wire, 10...Resin.
Claims (1)
所定の配線を有する配線用チップとを金属製リードフレ
ーム上にダイボンディングし、半導体チップ、配線用チ
ップおよびリードフレーム間の所定電極とを各々ワイヤ
ボンディング法により接続した後樹脂封止したことを特
徴とする混成集積回路装置。At least two semiconductor chips and a wiring chip having predetermined wiring on the silicon chip are die-bonded onto a metal lead frame, and the semiconductor chips, the wiring chip, and a predetermined electrode between the lead frames are each bonded using a wire bonding method. A hybrid integrated circuit device characterized in that it is resin-sealed after being connected by.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1218987A JPH0382069A (en) | 1989-08-24 | 1989-08-24 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1218987A JPH0382069A (en) | 1989-08-24 | 1989-08-24 | Hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0382069A true JPH0382069A (en) | 1991-04-08 |
Family
ID=16728495
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1218987A Pending JPH0382069A (en) | 1989-08-24 | 1989-08-24 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0382069A (en) |
-
1989
- 1989-08-24 JP JP1218987A patent/JPH0382069A/en active Pending
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