JPH0382038A - Manufacture of bipolar transistor - Google Patents

Abstract

PURPOSE:To make an element finer without increasing the number of processes and decrease both parasitic capacity and resistance by performing the formation of base electrodes with a lift-off process including self-alignment between emitter and base regions and forming even a base region as well simultaneously by self-alignment. CONSTITUTION:When a bipolar transistor having multilayer structure in which at least three layers consisting of the 1st conductivity type collector layer 23, the 2nd conductivity type base layer 24, and the 1st conductivity type emitter layer 25 are laminated in this order is manufactured, its manufacturing steps comprise: a process for the formation of an emitter mesa; processes for the formation of side wall films 32 at side walls of the emitter mesa as well as the base region 24 by using the foregoing emitter mesa and the side wall films 32 as masks; a process for replacing the side wall films 32 with base electrodes 34 by the use of resists 33 having each pattern at a base electrode extracting part. For example, after forming a collector contact layer 22, the collector 23, the base layer 24, the emitter layer 25, and an emitter cap layer 26 on a semiinsulating board 21, respective processes as mentioned above are performed.

Description

[Detailed Description of the Invention] Industrial Field of Application The present invention relates to a method for manufacturing a bipolar transistor that can be used as a semiconductor element with excellent high-speed performance and high-frequency characteristics required for advanced information processing and communication systems. With the development of an advanced information society in recent years, there is an increasing need for higher frequencies and higher densities in the communications field, as well as higher speeds and larger capacities in the information processing field.
In order to distantly relate to these, research and development is being actively conducted to reduce the resistance and capacitance components of semiconductor elements and improve performance such as high speed and high integration. Bipolar transistor (heterojunction bipolar transistor) 6 The ability to reduce base resistance and base-emitter capacitance without lowering current gain has attracted attention as a semiconductor device that enables high-speed operation. The conventional manufacturing method of bipolar transistors will be explained with reference to FIGS. 2(a) and (b) *
(c), (d), (e) e (f) and Fig. 3 (a), (b), (c) i. Figures (a), (b), (c), (d)t (e), (
In f), l is a semi-insulating group l! which becomes the substrate of the semiconductor device. ih2 is a collector contact layer serving as a collector extraction layer; 3 is a collector layer; 4 is a paste layer; 5 is an emitter layer made of a material with a larger band gap than the base layer 4; 6 is the contact resistance between the emitter layer 5 and the emitter electrode 8a. 7 is an insulating region formed for isolation between elements; 8 is a first ion beam lO using emitter mask pattern 9 as a mask;
The emitter electrode gold ML 11, which becomes the emitter electrode 8a by etching, is etched on the emitter mask pattern 9 and the first sidewall 12a for insulating the base electrode metal 12 and the emitter layer 5 when the base electrode metal 12 is formed. The paste gold IL 13 formed on the first sidewall 11 serves as a mask for forming the base electrode 12b by the second ion beam 14.
Reference numeral 5 denotes a third side wall for insulating the base layer 4 and the collector electrode 16.The method for manufacturing a conventional bipolar transistor with the above-described structure is described below as a first conventional example. A high concentration of nMI is applied on the semi-insulating substrate 1.
Collector contact layer 2 made of GaAs, and n
Collector layer 3a made of type GaAs, highly doped p-type GaAs
A base layer consisting of 4. L The emitter layer 5 made of N-type AI-, 5Ga-, and As and the emitter cap layer 6 made of high-concentration n-type GaAs are formed by ion implantation. The emitter electrode metal 8, which will become the emitter electrode, is formed on the entire surface by dry etching using the first ion beam 1O using the emitter mask pattern 9 as a mask (see Fig. 2).
a)) This line exposes the base layer 4 and forms an emitter mesa. This line emitter electrode 8a has an area equal to the emitter area.
is formed (FIG. 2(B)). Next, an insulating film is formed on the entire surface by anisotropic etching to form the first sidewall 11 on the side surface of the emitter mesa (FIG. 2(C)). A metal that will become a base electrode is deposited, a base electrode metal 12 is formed on the exposed base layer 4, and a base metal 12a is formed on the emitter mask pattern 9. A second side wall 1 is further formed on the side surface of the first side wall 11 by anisotropic etching.
Then, the collector contact layer 2 is exposed by anisotropic etching using the second ion beam 14 using the second sidewall 13 as a mask. Base metal 12a (t,,
The exposed portion of the base electrode metal 12 is etched and removed at the same time, and becomes the covered portion of the base electrode metal 12 by the second side wall 13 & the upper base electrode 12b (FIG. 2(e)).

Further, a third sidewall 15 is formed using the same method as described above, and a collector electrode 16 is formed on the collector contact layer 2 to complete a type tL bipolar transistor (FIG. 2(f)). (Example (L Hayama Rabuji Institute Op Electrical and Electronics Engineer-X Electron Device Letters
No. EDL-8! No. 5, pages 246-248 Trap 1
987 (IEEE Electron Devi
ceLetters, Vol, EDL-8,
No.

5, pp. 246-248 (1987)) As described above, the first side wall 11, the second side wall 13, and the third
By using the sidewalls 15, it is possible to form the emitter electrode 8a, the base electrode 12b, and the collector electrode 16 in a self-aligned manner with respect to the emitter mask pattern 9, which reduces parasitic resistance and simplifies the process. The second conventional example of the conventional bipolar transistor manufacturing method is shown in Figures 3(a), (b), and (c). for(
\ As will be explained below, in FIGS. 3(a), (b), and (c), 51 is a semi-insulating group K which becomes the substrate of the semiconductor device. 52 is the collector contact layer K which becomes the extraction layer of the collector. 53 is the collector ML.
54 is a base layer; 55 is an emitter layer; 56 is an emitter cap layer for reducing the contact resistance between the emitter layer 55 and the emitter electrode 57; 58 is a resist pattern 59
By pattern inversion using
A space electrode formed on the gold plate 62 is an insulating region for forming a base region, and a collector electrode 63 is formed on a semi-insulating substrate 51 made of GaAs with a high concentration n.
A collector contact layer 52 made of type GaAs, a collector layer 53 made of n-type GaAs, and a highly doped p-type GaA
An emitter electrode 57 is formed on the emitter cap layer 56 by forming a base layer 54 made of S, an emitter layer 55 made of N-type Al. An emitter mesa is formed by using the emitter electrode 57 as a mask.Next, after forming a sidewall film 58 on the emitter electrode 57 and the side surfaces of the emitter mesa, a resist is applied to the entire surface and the emitter electrode is flattened by dry etching. 57 and a resist pattern 59 exposing the upper part of the side wall M58 is formed (FIG. 3(a)). Next, the sidewall film 58 is removed by etching, and a metal that will become a resistor base electrode is deposited on the entire surface.A base electrode 60 is formed on the base layer 54, and a base electrode metal 61 is formed on the emitter electrode 57 and the resist pattern 59. (Fig. 3(b)). Next, the base electrode metal 61 on the resist pattern 59 is removed by a lift-off method using the resist pattern 59. An insulating region 62 that will form a base region is formed by an ion implantation method, and further on the collector contact layer 52. A collector electrode 63 is formed at the top, and the bipolar transistor is completed (Fig. 3(c)).
(No. 13809) As described above, by forming the base electrode 60 by inverting the pattern of the sidewall film 58, it is possible to form the base electrode 60 in self-alignment with the emitter mesa, thereby reducing parasitic resistance and improving the quality of the semiconductor device. Although improvements in performance such as faster speeds are expected, the invention still has problems to be solved, as shown in FIG. 2(a) as a first conventional example.

(b), (c), (d)t (e)
, by the method shown in (f) (y).
The collector electrode heat treatment (& the base electrode 12b and the base layer 4) may also be performed on the base electrode 12b at the same time. The temperature is higher than that of the base electrode heat treatment for reducing the contact resistance between the base electrode 12b and the base layer 4. 3(a) and (b) as a second conventional example.

It becomes possible to form the base electrode 60 after performing the collector electrode heat treatment on the collector electrode 63 by pattern reversing the pattern of the GEL side wall M58 and forming the base electrode 60 by the method shown in (C). Although the problem shown in the first conventional example can be improved, a new mask is required to form the insulating region 6 when forming the base region.
2, and the process for forming the mask is increased compared to the first conventional example.Furthermore, in consideration of the mask alignment margin, the base region is expanded by about 2 μm on both sides of the base electrode 60, and the base region is In view of the above problems, the base electrode is formed by a lift-off method that includes self-alignment between the emitter and the base, and the pace region is also formed by self-alignment at the same time. The present invention provides a method for manufacturing bipolar transistors that enables device miniaturization without increasing the number of steps and reduces parasitic capacitance and parasitic resistance. A method for manufacturing a bipolar transistor according to the present invention.
Manufacturing of a bipolar transistor having a multilayer film structure in which at least three layers of a base layer of a second conductivity type and an emitter layer of a first conductivity type are laminated in this order. A step of forming a paste region using the emitter mesa and the sidewall film as a mask; and a step of replacing the sidewall film with a base electrode using a resist having a pattern of a base electrode lead-out portion. The above-described method can significantly reduce the parasitic resistance and parasitic capacitance of a bipolar transistor without increasing the number of steps, thereby improving device characteristics such as high speed. A method of manufacturing a bipolar transistor as an example will be explained with reference to the drawings.
).

(g) It is a structural cross-sectional view showing each step of a method for manufacturing a bipolar transistor using a heterojunction according to an embodiment of the present invention. (d), (e), (f
).

(g) 1", 21 is a semi-insulating substrate that will be the substrate of the semiconductor device, 22 is the collector contact layer that will be the extraction layer of the collector, 23 is the collector layer, and 24 is the paste layer 25
26 is an emitter cap N made of a material with a larger band gap than the base layer 24; 26 is an emitter cap N for lowering the contact resistance between the emitter layer 25 and the emitter electrode 30; and 27 is the emitter cap N formed by forming an emitter region and reversing the pattern. 28 is an insulating region for isolation between elements.
9 is a first resist pattern for forming the emitter electrode 30 and the collector electrode 31; 321 is a side wall used for forming a pace region and forming a base electrode 34 using the second resist pattern 33 by pattern reversal; IL 34a is the second resist pattern 33
The first base electrode metal 34b formed on the emitter electrode 30 is the second base electrode metal formed on the emitter electrode 30, and the heterojunction in one embodiment of the present invention configured as described above is used. A method of manufacturing a bipolar transistor using a high concentration of n is deposited on a semi-insulating substrate 21 made of fGaAs.
Collector contact layer 22hn type G made of type GaAs
Collector layer 23 made of aAs and highly doped p-type GaAs
Base layer 2'4aN type A1, sGa@, MaA
An emitter mask pattern 27 for defining an emitter region is formed by dry etching a silicon oxide film (FIG. 1(a)).

Next, the base layer 24 is exposed by wet etching using the emitter mask pattern 27 as a mask to form an emitter mesa, and an insulating region 28 that serves as isolation between elements is formed by ion implantation (FIG. 1(b)).

Next, a collector electrode pattern was formed by flattening the surface using a resist spin code, and then dry etching was performed to expose the upper part of the emitter mask pattern 27, forming a fine resist pattern 29.
The collector contact layer 2 is removed by wet etching.
2 (Figure 1 (C)). Next, after removing the emitter mask pattern 27, a metal that will become the emitter and collector electrodes is vapor-deposited, and an emitter electrode 30 and a collector electrode 31 are formed by a lift-off method using the first resist pattern 29 (see FIG. 1). d)).

Next, a sidewall film 32 made of silicon oxide is formed on the side surfaces of the emitter electrode 30 and the emitter mesa, which have been heat-treated to reduce contact resistance.
2 as a mask, the exposed base layer 24 is removed by etching to form a base region (FIG. 1(e)).
. Next, a true-based extraction pattern is formed by flattening the surface using a resist spin code. Further, a second resist pattern 33 is formed by dry etching to expose at least the upper part of the sidewall film 32. Next, the sidewall The sidewall film 32 is replaced with the base electrode 34 by etching away the film 32 and depositing a metal that will become a base electrode on the entire surface to form a base electrode 34 on the base layer 24. A first base electrode metal 34a and a second space electrode metal 34b are formed on the second resist pattern 33 and the emitter electrode 30, respectively (FIG. 1(f)).As described above, the side wall Forming the base electrode 34 after removing the base electrode 832 by etching is also referred to as replacement.Next, the first base electrode metal 34a is removed by a lift-off method using the second resist pattern 33, and the bipolar transistor is completed. Figure 1 (g)).

As described above, in this embodiment, the base region L and the base electrode 34 are formed by self-alignment with the emitter mesa using the sidewall film 32, and the collector electrode 31 is subjected to collector electrode heat treatment (current collector electrode heat treatment and emitter electrode heat treatment). In this embodiment, the collector electrode heat treatment for the collector electrode 31 and the emitter electrode heat treatment for the emitter electrode 30 are performed at the same time. The contact resistance between the base electrode 34 and the base layer 24 is kept low, and a mask for forming the base region is not required.
By making it possible to miniaturize the element, the parasitic capacitance and parasitic resistance can be reduced, the inherent high-speed performance of bipolar transistors can be demonstrated, and the device characteristics can be significantly improved. In the example, the base region is formed by etching and removing the base layer 24 using the sidewall film 32 as a mask.The base region may be formed by preventing the exposed base layer 24 from acting as a base region. ,
For example, C'L may be insulated by implanting ions such as hydrogen. In this embodiment, the base electrode 34 is formed using the emitter mesa having the emitter electrode 30 and the second resist pattern 33 as a mask. Formation of electrode 34 GA side wall lI! For example, if the emitter mesa has a sufficient inverted mesa shape as shown in FIG. 1(b), the emitter electrode 30 on the emitter mesa is not necessary and the inverted mesa The emitter mesa having a sufficient shape and the second resist pattern 33 may be used as a mask.Effects of the Invention As described above, the method for manufacturing a bipolar transistor of the present invention (1) Collector of first conductivity type Second conductivity In manufacturing a bipolar transistor having a multilayer film structure in which at least three layers of a base layer and an emitter layer of a first conductivity type are laminated in this order, step a of forming an emitter mesa.
forming a sidewall film on the sidewall of the emitter mesa; forming a base region using the emitter mesa and the sidewall film as a mask; replacing the sidewall film with a base electrode using a resist having a pattern of a base electrode extraction part; By using the method for manufacturing a bipolar transistor of the present invention, which is characterized by including

[Brief explanation of drawings]

Figure 1 (a), (b), (c), (d), (e), (f
). (g) is a structural cross-section showing each step of the manufacturing method of a bipolar transistor in an embodiment of the present invention.
Figures (a), (b) e (c) e (d), (e),
(f) and Figures 3 (a), (b), ('c)J Turtle A structural cross-sectional view showing each step of the conventional bipolar transistor manufacturing method is 1.21.51...half. Insulating group [2,22゜52...
・Collector contact 凰 3. 23. 53-... Collector 凰 4. 24. 54...Base 凰 5゜25.55...Emitter 凰 6. 2.6. 56・
...Emitter cap 凰? , 28. 62...
Insulating region 8a, 30. 57... Emitter electric [9
, 27...Emitter mask pattern λ 11...First
side wall 12b, 34.60... base electric K 13.
...Second side wall 15...Third side wall 16. 31.
．． 63...Collector electrode 32.58...Side wall K
34b...Second pace electrode entire island

Claims (4)

[Claims] (1) Forming an emitter mesa in manufacturing a bipolar transistor having a multilayer structure in which at least three layers, a collector layer of a first conductivity type, a base layer of a second conductivity type, and an emitter layer of a first conductivity type are laminated in this order. The process of
a step of forming a sidewall film on the sidewall of the emitter mesa, forming a base region using the emitter mesa and the sidewall film as a mask, and a step of replacing the sidewall film with a base electrode using a resist having a pattern of a base electrode extension part. A method for manufacturing a bipolar transistor, comprising: (2) The method for manufacturing a bipolar transistor according to claim 1, wherein the base region is formed by etching and removing the base layer. (3) A method for manufacturing a bipolar transistor according to claim 1, characterized in that the base region is formed by ion implantation into the base layer. (4) The method for manufacturing a bipolar transistor according to claim 1, wherein at least the emitter layer of the collector layer and the emitter layer is made of a semiconductor material having a larger band gap than the base layer.