JPH0828376B2 - Bipolar transistor manufacturing method - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a bipolar transistor which can be used as a semiconductor device excellent in high speed performance and high frequency characteristics required for advanced information processing and communication systems. .

2. Description of the Related Art With the development of the advanced information society in recent years, higher frequencies and higher densities in the communication field and higher speeds and higher capacities in the information processing field are increasingly required. In order to achieve these, research and development for reducing the resistance component and the capacitance component of the semiconductor element and improving the performance such as high speed and high integration are being actively conducted. In particular, a bipolar transistor using a heterojunction whose emitter bandgap is larger than the base (heterojunction bipolar transistor) can reduce the base resistance and the capacitance between the base and the emitter without lowering the current gain. It is attracting attention as a semiconductor device that enables

Hereinafter, a conventional method for manufacturing a bipolar transistor will be described with reference to the drawings.

2 (a), (b), (c), (d), (e),
(F) and FIGS. 3 (a), (b) and (c) are structural sectional views showing a conventional method for manufacturing a bipolar transistor.

2 (a), (b), (c), (d), (e),
In (f), 1 is a semi-insulating substrate serving as a substrate of a semiconductor device, 2 is a collector contact layer serving as a collector extraction layer, 3 is a collector layer, 4 is a base layer, 5 is a band gap smaller than the base layer 4. An emitter layer made of a large material, 6 is an emitter cap layer for reducing the contact resistance between the emitter layer 5 and the emitter electrode 8a, 7 is an insulating region formed for element isolation, and 8 is an emitter mask pattern 9. An emitter electrode metal which becomes the emitter electrode 8a by etching with the first ion beam 10 used as a mask, 11 is a first side wall for insulating the base electrode metal 12 from the emitter layer 5, and 12a is the base electrode metal. 12
Base metal formed on the emitter mask pattern 9 and the first side wall 11 at the time of formation, 13 is a second side wall which serves as a mask for forming the base electrode 12b by the second ion beam 14, and 15 is the base Layer 4 and collector electrode 16
It is a third side wall for insulating between and.

A conventional method for manufacturing a bipolar transistor having the above structure will be described below as a first conventional example.

First, on a semi-insulating substrate 1 made of GaAs, a high concentration n-type
A collector contact layer 2 made of GaAs, a collector layer 3 made of n-type GaAs, a base layer 4 made of high-concentration p-type GaAs, an emitter layer 5 made of N-type Al _0.3 Ga _0.7 As, and a high-concentration n-type GaAs. After forming the emitter cap layer 6 made of
An insulating region 7 for element isolation is formed by ion implantation. Next, after forming the emitter electrode metal 8 to be the electrode of the emitter on the entire surface, dry etching is performed by the first ion beam 10 using the emitter mask pattern 9 as a mask (FIG. 2A), and the base layer 4 is formed. To expose the emitter mesa. At this time, an emitter electrode 8a having the same area as the emitter area is formed (FIG. 2 (b)). Next, an insulating film is formed on the entire surface, and a first side wall 11 is formed on the side surface of the emitter mesa by blue and anisotropic etching (FIG. 2 (c)). Next, a metal to be a base electrode is vapor-deposited, a base electrode metal 12 is formed on the exposed base layer 4, and a base metal 12a is formed on the emitter mask pattern 9. Then, the entire surface is insulated again. After the film is formed, a second film is further formed on the side surface of the first side wall 11 by anisotropic etching.
A side wall 13 is formed (FIG. 2 (d)). Next, the second
The collector contact layer 2 is exposed by anisotropic etching using the second ion beam 14 with the side wall 13 of FIG. At this time, the base metal 12a is removed at the same time as the exposed portion of the base electrode metal 12 is etched, and the base electrode metal 12a is removed by the second sidewall 13.
The covering portion of 12 becomes the base electrode 12b (FIG. 2 (e)).

Further, in the same manner as described above, after forming the third side wall 15, the collector electrode 16 is formed on the collector contact layer 2 to complete the bipolar transistor (FIG. 2 (f)). (For example, Hayama et al., The Institute of Electrical and Electronics Engineers, Electron Devices, Letters, EDL-8, No. 5, pp. 246-248, 1987 (I
EEE Electron Device Letters, Vol.EDL−8, No.5, pp2
46-248 (1987))).

As described above, by using the first side wall 11, the second side wall 13, and the third side wall 15, the emitter electrode 8a, the base electrode 12b, and the collector electrode 16 are self-aligned with the emitter mask pattern 9. Can be formed.
Therefore, the parasitic resistance is reduced and the process is simplified.
Performance improvements such as high speed and high integration of semiconductor elements are expected.

Next, a second conventional example of a conventional method for manufacturing a bipolar transistor will be described below with reference to FIGS. 3 (a), (b) and (c).

In FIGS. 3A, 3B and 3C, 51 is a semi-insulating substrate which is a substrate of a semiconductor device, 52 is a collector contact layer which is a collector extraction layer, 53 is a collector layer, and 54 is a collector layer.
Is a base layer, 55 is an emitter layer, 56 is an emitter cap layer for reducing the contact resistance between the emitter layer 55 and the emitter electrode 57, and 58 is for forming a base electrode 60 by pattern inversion using a resist pattern 59. A sidewall film, 61 is a base electrode metal formed on the resist pattern 59 and the emitter electrode 57 when the base electrode 60 is formed, 62 is an insulating region for forming a base region, and 63 is a collector electrode.

First, a high-concentration n-type is formed on a semi-insulating substrate 51 made of GaAs.
A collector contact layer 52 made of GaAs, a collector layer 53 made of n-type GaAs, and a base layer 54 made of high-concentration p-type GaAs.
And an emitter layer 55 made of N-type Al _0.3 Ga _0.7 As and an emitter cap layer 56 made of high-concentration n-type GaAs, and then an emitter electrode 57 is formed on the emitter cap layer 56.
An emitter mesa is formed using the emitter electrode 57 as a mask. Next, a sidewall film 58 is formed on the side surfaces of the emitter electrode 57 and the emitter mesa, and then a resist is applied to the entire surface to planarize it, and then the upper portions of the emitter electrode 57 and the sidewall film 58 are exposed by dry etching to form a resist pattern. 59 is formed (FIG. 3 (a)). Next, the sidewall film 58
After etching away, a metal to be a base electrode is vapor-deposited on the entire surface, and a base electrode 60 is formed on the base layer 54, and a base electrode metal 61 is formed on the emitter electrode 57 and the resist pattern 59. (FIG. 3 (b)). Next, the base electrode metal 61 on the resist pattern 59 is removed by a lift-off method using the resist pattern 59, and then an insulating area 62 to be a base area is formed by an ion implantation method. A collector electrode 63 is formed on the layer 52 to complete the bipolar transistor (FIG. 3 (c)). (For example, Japanese Patent Application No. 63-13809) As described above, by pattern-reversing the sidewall film 58 to form the base electrode 60, the base electrode 60 can be formed in self-alignment with the emitter mesa. . Therefore, the parasitic resistance is reduced, and it is expected that the performance of the semiconductor device such as speeding up will be improved.

Problems to be Solved by the Invention However, as a first conventional example, FIG.
In the methods shown in (b), (c), (d), (e), and (f), the collector electrode 16 is formed after the base electrode 12b is formed. The collector electrode heat treatment required to make low resistance contact with layer 2 is also performed on the base electrode 12b at the same time. The collector electrode heat treatment is performed on the base electrode 12
Since the temperature is higher than that of the heat treatment of the base electrode for reducing the contact resistance between b and the base layer 4, it is difficult to keep the contact resistance of the base electrode 12b and the base layer 4 reduced by the heat treatment of the base electrode low. It had a problem that

Furthermore, as a second conventional example, FIG. 3 (a), (b),
In the method as shown in (c), since the side wall film 58 is pattern-inverted to form the base electrode 60, the base electrode 60 can be formed after the collector electrode 63 is heat-treated. The problems shown in the first conventional example are improved. However, in forming the base region, it is necessary to provide a new mask to form the insulating region 62, the number of steps for forming the mask is increased as compared with the first conventional example, and the mask alignment margin is taken into consideration. The region spreads about 2 μm outside the base electrode 60, and there is a problem that it is difficult to miniaturize the base region.

In view of the above problems, the present invention forms a base electrode by a lift-off method that includes self-alignment between an emitter and a base, and simultaneously forms a base region by self-alignment, thereby increasing the number of steps of the device. The present invention provides a method for manufacturing a bipolar transistor which enables miniaturization and can reduce parasitic capacitance and parasitic resistance.

Means for Solving the Problems In order to solve the above problems, a method for manufacturing a bipolar transistor according to the present invention includes a first conductivity type collector layer, a second conductivity type base layer, and a first conductivity type emitter layer. In manufacturing a bipolar transistor having a multilayer film structure in which at least three layers are stacked in this order, a step of forming an emitter mesa, a sidewall film is formed on a sidewall of the emitter mesa, and etching is performed using the emitter mesa and the sidewall film as a mask. To define a base region and the step of replacing the sidewall film with a base electrode.

Action In the present invention, the parasitic resistance and the parasitic capacitance of the bipolar transistor can be significantly reduced by the above method without increasing the number of steps, and thus the device characteristics such as high speed can be improved.

Example Hereinafter, a method for manufacturing a bipolar transistor as an example of the present invention will be described with reference to the drawings.

1 (a), (b), (c), (d), (e),
(F) and (g) are structural cross-sectional views showing a method of manufacturing a bipolar transistor using a heterojunction in each embodiment of the present invention for each step.

1 (a), (b), (c), (d), (e),
In (f) and (g), 21 is a semi-insulating substrate serving as a substrate of a semiconductor device, 22 is a collector contact layer serving as a collector extraction layer, 23 is a collector layer, 24 is a base layer, and 25 is the base layer 24. An emitter layer made of a material having a larger band gap, 26 is the emitter layer 25 and the emitter electrode 30.
An emitter cap layer for lowering the contact resistance with 27, an emitter mask pattern 27 for forming the emitter electrode 30 by forming an emitter region and pattern inversion,
28 is an insulating region for element isolation, 29 is a first resist pattern for forming the emitter electrode 30 and the collector electrode 31, 32 is a second resist pattern by forming a base region and pattern inversion 33 Base electrode using
A sidewall film used to form 34, 34a is a first base electrode metal formed on the second resist pattern 33, 34a
b is a second base electrode metal formed on the emitter electrode 30.

A method for manufacturing a bipolar transistor using the heterojunction in the embodiment of the present invention configured as described above will be described below.

First, a high-concentration n-type is formed on a semi-insulating substrate 21 made of GaAs.
A collect contact layer 22 made of GaAs, a collector layer 23 made of n-type GaAs, and a base layer 24 made of high-concentration p-type GaAs.
And an emitter layer 25 made of N-type Al _0.3 Ga _0.7 As and an emitter cap layer 26 made of high-concentration n-type GaAs are formed, and then an emitter mask pattern 27 for defining an emitter region is formed by dry etching of a silicon oxide film. (FIG. 1 (a)). Next, the base layer 24 is exposed by wet etching using the emitter mask pattern 27 as a mask to form an emitter mesa, and then an insulating region 28 for element isolation is formed by ion implantation (FIG. 1 (b)). . Next, after flattening the surface by spin coating of a resist, a collector electrode pattern is formed, and then the emitter master pattern is formed by dry etching.
After exposing the upper portion of 27 to form the first resist pattern 29, the collector contact layer 22 is exposed by wet etching (FIG. 1 (c)). Next, after removing the emitter mask pattern 27, a metal to be electrodes of the emitter and the collector is vapor-deposited, and the first resist pattern is formed.
The emitter electrode 30 and the collector electrode 31 are formed by the lift-off method using 29 (FIG. 1 (d)). Then, after heat treatment for reducing the contact resistance, a silicon oxide film is formed on the entire surface, and anisotropic dry etching is performed to form the silicon oxide film on the side surfaces of the emitter electrode 30 and the emitter mesa. A side wall film 32 is formed, and the base layer 24 exposed by using the side wall film 32 as a mask is removed by etching to form a base region (FIG. 1 (e)). Next, after the surface is flattened by spin coating of a resist, a second resist pattern 33 exposing at least the upper portion of the sidewall film 32 is formed by dry etching. Next, the sidewall film 32 is removed by etching, a metal serving as a base electrode is deposited on the entire surface, and a base electrode 34 is formed on the base layer 24, thereby replacing the sidewall film 32 with the base electrode 34. . At this time, a first base electrode metal 34a and a second base electrode metal 34b are formed on the second resist pattern 33 and the emitter electrode 30, respectively (FIG. 1 (f)). As described above, the formation of the base electrode 34 after the sidewall film 32 is removed by etching is referred to as replacement.
Then, the first base electrode metal 34a is removed by a lift-off method using the second resist pattern 33 to complete a bipolar transistor (FIG. 1 (g)).

As described above, according to the present embodiment, the base region and the base electrode 34 are formed by self-alignment with the emitter mesa using the side wall film 32, and the collector electrode heat treatment (generally collector power supply heat treatment and emitter heat treatment) is performed on the collector electrode 31. Since the heat treatment for the power source is performed at the same temperature, the heat treatment for the collector power source for the collector electrode 31 and the heat treatment for the emitter electrode for the emitter electrode 30 are simultaneously performed in this embodiment.) Since the base electrode 34 is formed. , While maintaining a low contact resistance between the base electrode 34 and the base layer 24, and because a base region forming mask is not required, the base region does not spread outside from the base electrode 34, the second conventional It is formed about 4 μm shorter than the example, and the element can be miniaturized.

As a result, the parasitic capacitance and the parasitic resistance are reduced, the high-speed performance inherent in the bipolar transistor is exhibited, and the device characteristics can be greatly improved.

In this embodiment, the base region is formed by etching the base layer 24 using the sidewall film 32 as a mask, but the base region is formed so that the exposed base layer 24 does not act as the base region. For example, the insulation may be made by ion implantation of hydrogen or the like.

In this embodiment, the base electrode 34 is formed by forming the emitter mesa having the emitter electrode 30 and the second resist pattern.
33 was used as a mask, but the base electrode 34 was formed by
It may be replaced with the side wall film 32 and does not come into contact with the emitter mesa. For example, the emitter mesa is shown in FIG.
If the reverse mesa shape shown in FIG. 2 is sufficient, the emitter electrode 30 on the emitter mesa is not necessary, and the emitter mesa and the second resist pattern 33 having a sufficient reverse mesa shape are not necessary.
And may be used as a mask.

As described above, in the method for manufacturing a bipolar transistor of the present invention, at least three layers of the first conductivity type collector layer, the second conductivity type base layer, and the first conductivity type emitter layer are laminated in this order. In manufacturing a bipolar transistor having a multilayer film structure, a step of forming an emitter mesa, a step of forming a side wall film on a side wall of the emitter mesa, and a step of forming a base region by using the emitter mesa and the side wall film as a mask; Is replaced with a base electrode.

By using the bipolar transistor manufacturing method of the present invention, the parasitic resistance and the parasitic capacitance are reduced, and it is possible to obtain a bipolar transistor having excellent device characteristics such as high-speed performance.

[Brief description of drawings]

1 (a), (b), (c), (d), (e),
(F) and (g) are structural cross-sectional views showing a method of manufacturing a bipolar transistor in one embodiment of the present invention for each step, and FIGS. 2 (a), (b), (c), (d), (E),
(F) and FIGS. 3 (a), (b), and (c) are structural cross-sectional views showing a conventional method for manufacturing a bipolar transistor in each step. 1,21,51 …… Semi-insulating substrate, 2,22,52 …… Collector contact layer, 3,23,53 …… Collector layer, 4,24,54 …… Base layer, 5,25,55 …… Emitter layer, 6,26,56 ... Emitter cap layer, 7,28,62 ... Insulation region, 8a, 30,57 ... Emitter electrode, 9,27 ... Emitter mask pattern, 11 ... First sidewall , 12b, 34,60 …… Base electrode, 13 …… Second side wall, 1
5 …… Third side wall, 16,31,63 …… Collector electrode, 32,58…
… Sidewall film, 34b …… Second base electrode metal.

Claims (4)

[Claims] 1. In manufacturing a bipolar transistor having a multilayer film structure in which at least three layers of a first conductivity type collector layer, a second conductivity type base layer and a first conductivity type emitter layer are laminated in this order, an emitter mesa is formed. A step of forming a sidewall film on the sidewall of the emitter mesa, defining a base region by etching using the emitter mesa and the sidewall film as a mask, and replacing the sidewall film with a base electrode. A method of manufacturing a bipolar transistor, including: 2. A method of manufacturing a bipolar transistor according to claim 1, wherein the base region is defined by etching away the base layer. 3. The method of manufacturing a bipolar transistor according to claim 1, wherein the base region is defined by insulation by ion implantation into the base layer. 4. The method of manufacturing a bipolar transistor according to claim 1, wherein at least the emitter layer of the collector layer and the emitter layer is made of a semiconductor material having a band gap larger than that of the base layer.