JPH0828377B2 - Bipolar transistor manufacturing method - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a bipolar transistor which can be used as a semiconductor device excellent in high speed performance and high frequency characteristics required for advanced information processing and communication systems. .

2. Description of the Related Art With the development of the advanced information society in recent years, higher frequencies and higher densities in the communication field and higher speeds and higher capacities in the information processing field are increasingly required. In order to achieve these, research and development for reducing the resistance component and the capacitance component of the semiconductor element and improving the performance such as high speed and high integration are being actively conducted. In particular, a bipolar transistor using a heterojunction whose emitter bandgap is larger than the base (heterojunction bipolar transistor) can reduce the base resistance and the capacitance between the base and the emitter without lowering the current gain. It is attracting attention as a semiconductor device that enables

Hereinafter, a conventional method for manufacturing a bipolar transistor will be described with reference to the drawings.

2 (a), (b), (c) and FIG. 3 (a),
(B) and (c) are structural sectional views showing a conventional method for manufacturing a bipolar transistor.

In FIGS. 2A, 2 </ b> B, and 2 </ b> C, 1 is a semi-insulating substrate that serves as a substrate of a semiconductor device, 2 is an emitter contact layer that serves as an emitter extraction layer, and 3 is a bandgap from the base layer 4. An emitter layer made of a large material, 5 is a collector layer, 6 is a collector cap layer for reducing the contact resistance between the collector layer 5 and the collector electrode 11, and 7 is an external beam region 9 and a high resistance region by an ion beam 8.
Connector mask pattern for selectively forming 10,
12 and 13 are an emitter electrode and a base electrode, respectively.

A conventional method for manufacturing a bipolar transistor having the above structure will be described below as a first conventional example.

First, on a semi-insulating substrate 1 made of GaAs, a high concentration n-type
GaAs emitter contact layer 2 and N-type Al _0.3 Ga
_An emitter layer 3 made of _0.7 As, a base layer 4 made of high-concentration p-type GaAs, a collector layer 55 made of n-type GaAs, and a collector cap layer 6 made of high-concentration n-type GaAs are formed. Next, after forming a collector mask pattern 7 for determining a collector region, selective ion implantation of an ion beam 8 composed of beryllium and oxygen is performed using the collector mask pattern 7 (FIG. 2A), and the collector mask pattern 7 is formed. After the removal, the beryllium-implanted high-concentration p-type external base region 9 and the oxygen-implanted high-resistance region 10 are formed by annealing.
Then, after performing wet etching for forming electrodes of the base and the emitter (FIG. 2 (b)), the emitter contact layer 2, the external base region 9 and the collector cap layer 6 are respectively etched. Forming an emitter electrode 12, a base electrode 13 and a collector electrode 11,
A bipolar transistor is completed (Fig. 2 (c)).
(For example, Adachi et al., The Institute of
Electrical and Electronics Engineers, Electron Device Letters, EDL-
Volume 7, Issue 1, pages 32-34, 1986 (IEEE Electron
Device Letters, Vol.EDL-7, No.1, pp32-34 (198
See 6))).

As described above, by performing selective ion implantation using the collector mask pattern 7, the external base region 9 and the high resistance region 10 are self-aligned and close to the collector region.
Can be formed. The high resistance region 10 suppresses the base current immediately below the external base region 9 and reduces the base-emitter capacitance, and the low resistance external base region 9 reduces the parasitic resistance of the base. It is expected that the performance will be improved by increasing the speed of the device.

Next, a second conventional example of a conventional method for manufacturing a bipolar transistor will be described below with reference to FIGS. 3 (a), (b) and (c).

In FIGS. 3A, 3B, and 3C, 51 is a semi-insulating substrate that serves as a substrate of a semiconductor device, 52 is an emitter contact layer that serves as an emitter extraction layer, and 53 is a bandgap that is closer to the base layer than the base layer. 53a, an emitter layer made of a large material
Is a high resistance region in which the outside of the emitter layer 53 has a high resistance,
55 is a collector layer, 56 is the collector layer 55 and collector electrode
57 Collector cap layer to reduce contact resistance with 57, 58
Is a sidewall film for forming the base electrode 60 by pattern inversion using the resist pattern 59, 61 is the base electrode
A base electrode metal is formed on the resist pattern 59 and the collector electrode 57 when forming 60, 62 is an insulating region for forming a base region, and 63 is an emitter electrode.

First, a high-concentration n-type is formed on a semi-insulating substrate 51 made of GaAs.
GaAs emitter contact layer 52 and N-type Al _0.3 Ga
After forming an emitter layer 53 made of _0.7 As, a base layer 54 made of high-concentration p-type GaAs, a collector layer 55 made of n-type GaAs, and a collector cap layer 56 made of high-concentration n-type GaAs, the collector cap is formed. A collector electrode 57 is formed on the layer 56, a connector mesa is formed by etching, and a high resistance region 53a is formed by ion implantation using the collector electrode 57 as a mask. Next, after forming a side wall film 58 on the side surfaces of the collector electrode 57 and the koremutamesa, a resist is applied on the entire surface to be planarized, and then a resist is formed by exposing the upper portions of the collector electrode 57 and the side wall film 58 by dry etching. A pattern 59 is formed (Fig. 3 (a)).
Next, after removing the sidewall film 58 by etching, a metal serving as a base electrode is vapor-deposited on the entire surface, and a base electrode 60 is formed on the base layer 54, and a base electrode is formed on the collector electrode 57 and the resist pattern 59. Metals 61 are respectively formed (FIG. 3 (b)).

Next, the base electrode metal 61 on the resist pattern 59 is removed by a lift-off method using the resist pattern 59, and then an insulating region 62 for forming a base region is ion-implanted using a mask (not shown). Then, an emitter electrode 63 is formed on the emitter contact layer 52 to complete a bipolar transistor (FIG. 3 (c)). (For example, Japanese Patent Application No. 63-13809) As described above, by pattern-reversing the side wall film 58 to form the base electrode 60, the base electrode 60 can be formed in self-alignment with the collector mesa. . Therefore, the parasitic resistance is reduced, and it is expected that the performance of the semiconductor device such as speeding up will be improved.

Problems to be Solved by the Invention However, as a first conventional example, FIG.
In the method shown in (b) and (c), the base electrode 13
Is formed by the lift-off method of the electrode metal which requires mask alignment, the external base region 9 needs to have a width of about 4 μm or more in consideration of the mask alignment margin even if the width of the base electrode 13 is 2 μm. It is difficult to reduce the parasitic capacitance between the base and the emitter by the external base region 9, and the emitter electrode from the emitter region directly below the collector corresponding to the width of the external base region 9
The distance to 12 is also about 4 μm or more, and it is difficult to reduce the parasitic resistance of the emitter.

Furthermore, as a second conventional example, FIG. 3 (a), (b),
In the method as shown in (c), since the base electrode 60 is formed by self-alignment with the collector mesa using the sidewall film 58,
The width of the base electrode 60 is about 1 μm, and the distance between the base electrode 60 and the collecta mesa is 0.2 μm.
It is possible to achieve about m, and it is possible to further miniaturize the structure as compared with the first conventional example. However, in forming the base region, it is necessary to provide a new mask to form the insulating region 62, and like the first conventional example, the external base region (not shown in FIG. About 3 μm or more is required for the base region (that is, the region excluding the region directly under the collector layer 55) of the base region in FIG. 6C, and it is difficult to reduce the parasitic capacitance between the base and the emitter. Along with this, the distance from the emitter region directly under the collector to the emitter electrode 63 is also about 3 μm or more, and it is difficult to reduce the parasitic resistance of the emitter.

In view of the above problems, the present invention forms a base electrode by performing a lift-off method including self-alignment with a collector mesa, and at the same time forms a base region by self-alignment, which enables further miniaturization of an element, Accordingly, the present invention provides a method for manufacturing a bipolar transistor capable of further reducing parasitic capacitance and parasitic resistance.

Means for Solving the Problems In order to solve the above problems, a method for manufacturing a bipolar transistor according to the present invention includes a first conductivity type emitter layer, a second conductivity type base layer, and a first conductivity type collector layer. In manufacturing a bipolar transistor having a multilayer film structure in which at least three layers are stacked in this order, a step of forming a collector mesa, forming a sidewall film on a sidewall of the collector, and using the collector mesa and the sidewall film as a mask,
The method includes a step of defining a base region by etching, and a step of replacing the side wall film with a base electrode by using a resist having a pattern of a base electrode lead portion.

Effect In the present invention, the parasitic resistance and the parasitic capacitance of the bipolar transistor can be significantly reduced by the above method, and thus the device characteristics such as high speed can be improved.

Example Hereinafter, a method for manufacturing a bipolar transistor as an example of the present invention will be described with reference to the drawings.

1 (a), (b), (c), (d), (e),
(F) is a structural cross-sectional view showing, for each step, a method for manufacturing a bipolar transistor using a heterojunction in one embodiment of the present invention.

1 (a), (b), (c), (d), (e),
In (f), 21 is a semi-insulating substrate serving as a substrate of a semiconductor device, 22 is an emitter contact layer serving as an emitter extraction layer, 23 is an emitter layer made of a material having a bandgap larger than that of the base layer 24, and 25 is a collector layer. , 26 is a collector cap layer for reducing the contact resistance between the collector layer 25 and the collector electrode 31, 27 is a collector mask pattern for forming the collector electrode 31 by forming a collector region and pattern inversion, and 28 is ion implantation Formed of the external base region, 29 is an insulating region for element isolation, 30 is a first resist pattern for forming the collector electrode 31, 32 is a second resist pattern formed by base region formation and pattern inversion. A side wall film used for forming the base electrode 35 using the resist pattern 34, 33 is an emitter electrode,
Reference numeral 35a is a base electrode metal formed on the collector electrode 31.

A method for manufacturing a bipolar transistor using the heterojunction in the embodiment of the present invention configured as described above will be described below.

First, a high-concentration n-type is formed on a semi-insulating substrate 21 made of GaAs.
GaAs emitter contact layer 22 and N-type Al _0.3 Ga
After forming the emitter layer 23 made of _0.7 As, the base layer 24 made of high-concentration p-type GaAs, the collector layer 25 made of n-type GaAs, and the collector cap layer 26 made of high-concentration n-type GaAs, the collector region is formed. A collector mask pattern 27 to be determined is formed by dry etching of a silicon oxide film (FIG. 1 (a)). Then, selective ion implantation of Be and annealing are performed using the collector mask pattern 27 as a mask to form an external base region 28 including a part of the emitter layer 23 as p-type, and then the external base region 28 is wet-etched to form the external base region 28. An exposed collector mesa is formed, and an insulating region 29 for element isolation is formed by ion implantation (FIG. 1 (b)). Next, after the surface is flattened by spin coating of a resist, the upper portion of the collector mask pattern 27 is exposed by dry etching, and the collector mask pattern 27 is removed by wet etching to form a first resist pattern 30 ( FIG. 1 (c)).
Next, a metal to be a collector electrode is vapor-deposited, and a collector electrode 31 is formed by a lift-off method using the first resist pattern 30. Next, a silicon dioxide film is formed on the entire surface, and anisotropic dry etching is performed to form a side wall film 32 made of the silicon oxide film on the side surfaces of the collector electrode 31 and the collector mesa. Using the collector mesa having the collector electrode 31 on the upper portion as a mask, the exposed external base region 28 is removed by etching to form a base region (FIG. 1 (d)). Next, the emitter contact layer 22 is exposed by wet etching using a resist pattern (not shown) having an open emitter electrode pattern, and an emitter electrode 33 is formed by a lift-off method.
Next, after the surface is flattened by spin coating with a resist, a second resist pattern 34 exposing at least the upper portion of the sidewall film 32 is formed by dry etching (FIG. 1 (e)). Next, after removing the sidewall film 32 by etching, a metal to be a base electrode is deposited on the entire surface, and a base electrode 35 is formed by a lift-off method using the second resist pattern 34. Is replaced with the base electrode 35 to complete a bipolar transistor. At this time, the base electrode metal is formed on the collector electrode 31.
35a is formed (FIG. 1 (f)). Note that, as described above, the base electrode 35 after the sidewall film 32 is removed by etching.
Forming is called substitution.

As described above, according to the present embodiment, the base region and the base electrode 34 are formed by self-alignment with the collector mesa using the sidewall film 32, so that the mask for forming the base region and the base electrode 34 is formed. Is unnecessary, and the width of the external base region 28 can be set to about 1 μm, which is almost the same as the width of the base electrode 34, and the distance from the emitter region immediately below the collector to the emitter electrode 33 also has a mask alignment margin of 1 μm. Considering this, the size becomes about 2 μm, and the device can be miniaturized.

As a result, the parasitic resistance and the parasitic capacitance are reduced, the high-speed performance inherent in the bipolar transistor is exhibited, and the device characteristics can be greatly improved.

In this embodiment, the base region is formed by etching away the external base region 28 using the collector mesa and the sidewall film 32 as a mask, but the base region is formed by exposing the exposed external base region 28 to the base region. It is sufficient to prevent it from acting as, for example, it may be insulated by ion implantation of hydrogen or the like.

Further, in this embodiment, the base electrode 35 is formed by using the collector mesa having the collector electrode 31 and the second resist pattern 34 as a mask. However, the base electrode 35 is formed by replacing the side wall film 32, and It does not have to be in contact with the collector mesa. For example, if the collector mesa has a sufficient reverse mesa shape in FIG. 1B, the collector electrode 31 on the collector mesa is not necessary, and the collector mesa has a sufficient reverse mesa shape. The collector mesa and the second resist pattern 34 may be used as a mask.

As described above, in the method for manufacturing a bipolar transistor of the present invention, at least three layers of the first conductivity type emitter layer, the second conductivity type base layer, and the first conductivity type collector layer are laminated in this order. In manufacturing a bipolar transistor having a multilayer film structure, a step of forming a collector mesa, a step of forming a side wall film on a side wall of the collector mesa, and a step of forming a base region by using the collector mesa and the side wall film as a mask; Is replaced with a base electrode.

By using the bipolar transistor manufacturing method of the present invention, the parasitic resistance and the parasitic capacitance are reduced, and it is possible to obtain a bipolar transistor having excellent device characteristics such as high-speed performance.

[Brief description of drawings]

1 (a), (b), (c), (d), (e),
(F) is a structural cross-sectional view showing each step of the method for manufacturing a bipolar transistor in one embodiment of the present invention, FIGS. 2 (a), (b), (c) and FIG. 3 (a),
(B), (c) is a structural cross-sectional view showing a conventional method of manufacturing a bipolar transistor for each step. 1,21,51 …… Semi-insulating substrate, 2,22,52 …… Emitter contact layer, 3,23,53 …… Emitter layer, 4,24,54 …… Base layer, 5,25,55 …… Collector layer, 6,26,56 …… Collector cap layer, 7,27 …… Collector mask pattern, 9,28 …… External base region, 10,53a …… High resistance region, 11,31,57 …… Collector electrode , 12,33,63 …… Emitter electrode, 13,35,60 ……
Base electrode, 29,62 ... Insulating area, 32,58 ... Side wall film, 35
a, 61 …… Base electrode metal.

Claims (4)

[Claims] 1. A bipolar transistor having a multi-layer structure in which at least three layers of a first conductivity type emitter layer, a second conductivity type base layer and a first conductivity type collector layer are laminated in this order, and a collector mesa is manufactured. A step of forming a side wall film on the side wall of the collector mesa, defining a base region by etching using the collector mesa and the side wall film as a mask, and using a resist having a pattern of a base electrode extraction part. And a step of replacing the side wall film with a base electrode. 2. A method of manufacturing a bipolar transistor according to claim 1, wherein the base region is defined by etching away the base layer. 3. The method of manufacturing a bipolar transistor according to claim 1, wherein the base region is defined by insulation by ion implantation into the base layer. 4. The method of manufacturing a bipolar transistor according to claim 1, wherein at least the emitter layer of the collector layer and the emitter layer is made of a semiconductor material having a bandgap larger than that of the base layer.