JPS5875870A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the irregularity in the base widths of lateral transistors and to decrease the parasitic capacity of a semiconductor device by applying a self- aligning method with polycrystalline silicon. CONSTITUTION:An n type silicon accumulated layer 33 is formed on an n type buried layer 32, is formed in a projection, as shown, and p type polycrystalline silicons 35, 36 are formed on the side surfaces. A thick oxidized film 34 is increased directly under the polycrystalline silicon. A p type region 37 is formed in the layer 33. A p type region 37 is an emitter region, the layers 35, 36 are collector leading electrodes, diffused regions 351, 361 which are contacted with the polycrystalline layers are collector regions. The position of a diffusion window 39 for forming the region 37 is determined by a self-aligning method. Accordingly, the base width L of the transistor can be accurately determined. Further, the parasitic capacity can be reduced using the polycrystalline silicon.

Description

[Detailed description of the invention] The present invention relates to the structure of a semiconductor device.

The structure of a conventional lateral transistor is shown in FIG.

Here, a pnp transistor will be explained.

A silicon n-type deposited layer 13 is provided from the n-type buried layer 12, and an oxide film 14 is formed on a part thereof to form an isolation region. P-type diffusion layers 15 and 16 are provided in the n-type deposited layer 13 and connected to the electrode 11. As a result, the p-type diffusion layers 15 and 16 are emittered,
A conventional lateral PnP transistor is formed with the collector region as the collector region and the n-type layer 13 as the base region. In such a transistor structure, when the transistor operates, carriers injected from the emitter side accumulate in the base region 13 directly below the p-type emitter region, hindering high-speed operation. Furthermore, since the large collector region 16 and the base region are in contact with each other through a pn junction, the parasitic capacitance is large and the emitter is large.

Ta grounding lotus cutting frequency! , ~10MHz can only be obtained.

FIG. 2 shows a structure in which the lead electrode is made of polycrystalline silicon and the pn junction is made as small as possible in order to reduce parasitic capacitance and achieve high-speed operation.

In such a transistor structure, the p-type polycrystalline lead electrode 25
．． Since the thick oxide film 24 is formed directly under the n-type base region 26, the number of carriers injected into the n-type base excitation region 23 is extremely small. However, the base width of the lateral transistor is limited to the p-type region 25 diffused from the polycrystalline silicon 25 and 26.
and 26. As a result, the base width of the transistor changes due to the variation in the distance between the connection points between the polycrystalline layers 25 and 2.6 and the single crystal layer 23 and the variation in the diffusion depth of the p-type region 25.26. There is a drawback that the characteristic current amplification factor varies widely.

An object of the present invention is to eliminate the above-mentioned drawbacks, reduce variations in the base width of lateral transistors, and propose an element structure with less parasitic capacitance. In the following, embodiments of the present invention will be described, in which the above objects have been achieved by device fabrication techniques including a self-alignment method.

FIG. 3 is a sectional view of an element structure according to the present invention.

An n-type silicon deposit layer 33 is formed on the n-type buried layer 32, and as shown in FIG. Note that a thick oxide film 34 is inserted directly under the polycrystalline silicon. Furthermore, a p-type region 37 is formed within the n-type layer 33 . In the structure of the present invention, the p-type region 37 is an emitter region, and the polycrystalline layer 35.3
6 is a collector extraction electrode, and a diffusion region 3 in contact with the polycrystalline layer
5°36 is a collector area. Note that the position of the diffusion window 39 for forming the p-type region 37 is determined by a self-alignment method. Therefore, the base width of the transistor can be determined accurately.

FIG. 4 shows a manufacturing process for realizing the structure shown in FIG. 3. A detailed explanation will be given of a) to e).

a): An n-type deposited layer 43 is formed on a substrate having an n-type buried layer 42, and an oxide film 410 and a silicon dust film (813N
) 411, an oxide film 41'2 is formed.

Next, an oxide film, a dust film, and an oxide film are formed using the usual photolithography method, and drying and etching methods.

The silicon single crystal region is left in the rectangular convex shape shown in the figure. After thermally oxidizing and depositing the dust film, dry etching and etching methods are again used to leave the oxide film 413 and dust films 4 and 14 on the side surfaces of the convex shape.

b); Perform thermal oxidation to form a thick oxide film 44, and form a dust film 414. The oxide film 413 is removed to expose the silicon region on the side surface of the convex shape. Next, a polycrystalline silicon layer is deposited, and only the polycrystalline silicon layer on the upper surface of the convex shape is selectively removed, leaving polycrystalline silicon layers 45 and 46. Note that, in order to selectively remove the polycrystalline silicon layer, for example, a photoresist is buried in the concave plane portion, and the polycrystalline silicon on the upper part of the convex surface that has been sprayed out is removed. Next, from the polycrystalline silicon layer, p
By diffusing type impurities, p-type collector regions 451 and 461 are formed.
form.

C): Etch the dust film 411 from the side using a phosphoric acid solution heated to 160 to 180°C.

d): When the oxide film 412 is removed, the polycrystalline silicon is finely turned, and thermal oxidation is performed, the polycrystalline silicon layer 44 is removed.
．． An oxide film 415 is formed on the single crystal layer 45 and the single crystal layer 43. At this time, a sufficient difference in film thickness from the oxide film 410 that was initially formed is taken. (e): Remove the dust film 411, remove the thin mono-oxide film 410, diffuse pH and impurities, form a p-type region 47, and create an emitter region.

A part of the oxide film 415 is opened and polycrystalline silicon and pm
! A metal electrode 48 is formed in contact with region 47 .

Through the above manufacturing process, the device force of the present invention can be formed, but since the side etching method of the dust film is used to define the space between the p-type collector regions 451, 461 and the emitter region 47, controllability is improved. Good strength.

Base width can be determined accurately.

FIG. 5 is a sectional view of an embodiment of an element structure according to the present invention in which the base terminal is taken out near the element.

In this embodiment, the space region of the n-type buried layer 52 formed in the p-type substrate 51 and serving as I/I is n11. 'It is taken out from the surface through an n-type region 561 which is diffused from the polycrystalline layer 56 into the n-type layer 5.3. Note that the emitter, rib and collector regions may be either the p-type region 551 diffused from the p-type polycrystalline silicon layer 55 on the insulating film 54 or the p-type region 57 diffused from the top surface. In this embodiment, since the base terminal is taken out from the vicinity of the element, the base resistance is reduced and a miniaturized element can be realized.

FIG. 6 is a cross-sectional structural diagram of an element according to the embodiment of the present invention shown in FIG. 3, which pursues even higher speed.

In this embodiment, the conductivity type and cross-sectional shape are the same as those in the embodiment of FIG. 3, but a slightly higher concentration n-type region 616 is diffused around the p-type emitter region. n-type region 616
and p-type region 67 are diffused through the same opening.

Therefore, the carriers injected from the en and yen regions are 61
6 region receives an accelerating electric field and enters the collector region, resulting in high speed.

11:'- As described above, according to the present invention 1', the base width of a lateral transistor can be determined with good controllability, which is highly effective in reducing variations in device characteristics and realizing high-speed and fine devices.

It goes without saying that even in structures where the p-type region and the n-type region are changed in one text, the device characteristics are the same.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional structure diagram of a conventional lateral transistor, FIG. 2 is a cross-sectional diagram of a conventional lateral transistor with high frequency characteristics omitted, FIG. 3 is a cross-sectional diagram of a device according to the present invention, and FIG. Cross-sectional structure diagrams for each manufacturing process to realize the device shown in the figure,
FIG. 5 is a cross-sectional view of an element structure according to the present invention, in which the base electrode is directly connected to the surface, and FIG. 6 is a cross-sectional view of a structure in which the element of FIG. 3 is made faster.・32: N-type buried layer 33: N-type layer 34: Insulating film 35. 36: Polycrystalline layer 37: P-type layer 38: Electrode Fig. 1 5 Fig. 2 Fig. 3 Ryo 6

Claims (1)

[Claims] 1. A semiconductor substrate having a convex portion of a first conductivity type, and an insulating film provided on a portion other than the convex region of the substrate. a first region of a second conductivity type semiconductor layer of a conductivity type opposite to the first conductivity type provided on the insulating film and in contact with the base;
a second region of the second conductivity type provided within the base and in contact with the first region; and a third region of the second conductivity type provided within the base.
A semiconductor device characterized by having a region. 2. The semiconductor device according to claim 1, wherein the second region is divided into a fourth region of the first conductivity type and a fifth region of the second conductivity type. 3. The semiconductor device according to claim 1, further comprising a sixth region of the first conductivity type formed around the third region.