JPH0380549A - Mounting of semiconductor element - Google Patents
Mounting of semiconductor elementInfo
- Publication number
- JPH0380549A JPH0380549A JP1218083A JP21808389A JPH0380549A JP H0380549 A JPH0380549 A JP H0380549A JP 1218083 A JP1218083 A JP 1218083A JP 21808389 A JP21808389 A JP 21808389A JP H0380549 A JPH0380549 A JP H0380549A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- die
- circuit board
- polymer film
- conductive polymer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 63
- 238000000034 method Methods 0.000 claims abstract description 23
- 229920001940 conductive polymer Polymers 0.000 claims abstract description 21
- 239000000853 adhesive Substances 0.000 claims abstract description 18
- 230000001070 adhesive effect Effects 0.000 claims description 17
- 229920001187 thermosetting polymer Polymers 0.000 abstract description 7
- 238000010438 heat treatment Methods 0.000 abstract description 6
- 229910000679 solder Inorganic materials 0.000 abstract description 6
- 239000011248 coating agent Substances 0.000 abstract description 3
- 238000000576 coating method Methods 0.000 abstract description 3
- 238000004080 punching Methods 0.000 abstract description 3
- 230000035939 shock Effects 0.000 abstract description 2
- 238000010338 mechanical breakdown Methods 0.000 abstract 1
- 238000003466 welding Methods 0.000 abstract 1
- 230000006378 damage Effects 0.000 description 7
- 230000002950 deficient Effects 0.000 description 7
- 238000002844 melting Methods 0.000 description 6
- 230000008018 melting Effects 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- HSFWRNGVRCDJHI-UHFFFAOYSA-N alpha-acetylene Natural products C#C HSFWRNGVRCDJHI-UHFFFAOYSA-N 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229920001197 polyacetylene Polymers 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229920006254 polymer film Polymers 0.000 description 1
- 229920000128 polypyrrole Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/79—Apparatus for Tape Automated Bonding [TAB]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Abstract
Description
【発明の詳細な説明】
〔概要〕
ダイの表面に表面電極を、その反対裏面に裏面電極を備
える半導体素子の実装方法に係り、とくにテープキャリ
アを用いて多数の表面電極を一括ボンディングする方法
に関し、
半導体素子のテープキャリアによるボンディング時の加
圧力による衝撃を緩衝し機械的破壊を減少することと、
回路゛基板に固着された不良のた半導体素子を外し易く
することを目的とし、ダイの表面に表面電極を、その反
対裏面に裏面電極を備える半導体素子を回路基板上に実
装する工程中において、前記ダイの裏面全面に導電性ポ
リマー膜を予め形成した後、前記表面電極にテープキャ
リアをインナーリードボンディングする工程と、前記回
路基板の配線ランドを含む前記ダイ裏面全面との対向面
上に導電性ポリマー膜を予め形成し、さらにその上に導
電性接着剤を塗布した後、テープキャリアを用いてイン
ナーリードボンディングされた半導体素子を配線ランド
にフェイスアップでアウターリードボンディングすると
ともに、ダイを前記接着剤で固着する工程との両工程を
含むか、あるいはどちらか一方の工程を含むように構成
する。[Detailed Description of the Invention] [Summary] The present invention relates to a method of mounting a semiconductor element having a front electrode on the front surface of a die and a back electrode on the opposite back surface, and particularly relates to a method of collectively bonding a large number of front electrodes using a tape carrier. , to reduce mechanical damage by buffering the impact caused by the pressing force during bonding by the tape carrier of the semiconductor element;
During the process of mounting a semiconductor element on a circuit board, which has a front electrode on the front surface of the die and a back electrode on the opposite back surface, for the purpose of making it easier to remove a defective semiconductor element stuck to the circuit board, After forming a conductive polymer film on the entire back surface of the die in advance, bonding a tape carrier to the surface electrode by inner lead, and forming a conductive polymer film on the surface opposite to the entire back surface of the die including the wiring land of the circuit board. After forming a polymer film in advance and applying a conductive adhesive thereon, the inner lead-bonded semiconductor element is face-up outer lead-bonded to the wiring land using a tape carrier, and the die is bonded to the adhesive. It is configured to include both the process of fixing with the metal, or to include either one of the processes.
本発明はダイの表面に表面電極を、その反対裏面に裏面
電極を備える半導体素子の実装方法に係り、とくにテー
プキャリアを用いて多数の表面電極を一部ボンディング
する方法に関する。The present invention relates to a method for mounting a semiconductor element having a front electrode on the front surface of a die and a back electrode on the opposite back surface, and particularly relates to a method for partially bonding a large number of front electrodes using a tape carrier.
Ｔ Ａ Ｂ （Ｔａｐｅ Ａｕｔｏｍａｔｅｄ Ｂｏｎ
ｄｉｎｇ）技術においては、テープキャリアのインナー
リードを半導体素子の表面電極に接合するｅ （Ｉｎｎ
ｅｒ １ｅａｄ Ｂｏｎｄｉｎｇと言いＩＬＢと略記す
る）
つぎに、半導体素子のアクティブ領域の存在する面を上
にして（フェイスアンプと言う）アウターリードを回路
基板の配線ランドに接合する（Ｏｕ ｔｅｒ １ｅａｄ
Ｂｏｎｄｉｎｇと言いＯＬＢと略記する）とともにダ
イ自体を回路基板に接合材によりダイボンディング（Ｄ
ｉｅ Ｂｏｎｄｉｎｇ） Ｌ／ている。T A B (Tape Automated Bon
In the e (Inn ding) technology, the inner leads of the tape carrier are bonded to the surface electrodes of the semiconductor element.
Next, the outer leads (referred to as face amplifiers) are bonded to the wiring lands of the circuit board with the side where the active area of the semiconductor element is facing up.
Bonding (abbreviated as OLB) and die bonding (D
ie Bonding) L/It is.
ＩＬＢの工程においては、半導体素子の表面電極上に、
あるいはテープキャリアのインナーリード上に形成され
た金バンブなどの接合材を介して熱圧着により接合する
ため、半導体素子に機械的衝撃を与え、時には破壊する
問題がある。In the ILB process, on the surface electrode of the semiconductor element,
Alternatively, because the bonding is performed by thermocompression bonding via a bonding material such as a gold bump formed on the inner lead of the tape carrier, there is a problem that mechanical shock is applied to the semiconductor element, and sometimes it may be destroyed.
一方、実装された半導体素子の中に不良が発見された場
合にその半導体素子を取り外す必要が生じるが、その場
合テープキャリアのアウターワードは錫−鉛系の低融点
半田で接合される例が多いので対象とするアウターリー
ドだけを部分的に加熱溶融して容易に外すことができる
。しかし、半導体素子のダイは熱硬化性樹脂系の接着剤
で固着される場合が多いため容易に外すことができず半
導体素子を破壊してしまったり、外す必要のない別の半
導体素子や回路基板の基材を損傷し、高価な回路基板が
一部の半導体素子の不具合によって不良品となってしま
い回路基板の歩留まりが悪くなる結果を招いている。On the other hand, if a defective semiconductor element is found in a mounted semiconductor element, it becomes necessary to remove the semiconductor element, but in this case the outer word of the tape carrier is often joined with tin-lead based low melting point solder. Therefore, it is possible to easily remove only the target outer lead by partially heating and melting it. However, since the die of a semiconductor element is often fixed with thermosetting resin adhesive, it cannot be easily removed and the semiconductor element may be destroyed, or another semiconductor element or circuit board that does not need to be removed may be removed. This has resulted in damage to the base material of the circuit boards, resulting in expensive circuit boards becoming defective products due to defects in some of the semiconductor elements, and resulting in poor yields of circuit boards.
そのため、ボンディング時の素子破壊を減少することと
、手直しのし易いグイボンディングの方法が要求されて
いる。Therefore, there is a need for a method of bonding that reduces element destruction during bonding and that is easy to modify.
第３図の要部側断面図に示すように、ダイｌ１ａの表面
に表面電極１１ａ−Ｈ信号用あるいは電源用電極）を、
その反対裏面全面に裏面電極１１ａ−２（接地用電極あ
るいは電源用電極）を備える半導体素子１１ （高速信
号を扱う素子などは裏面全面に裏面電極を形成している
例が多い）を回路基板１２にテープキャリア１３を用い
て実装する場合、従来は先ずＩＬＢを行ってからＯＬＢ
を行う。As shown in the side cross-sectional view of the main part in FIG.
The circuit board 12 is a semiconductor element 11 having a back electrode 11a-2 (grounding electrode or power supply electrode) on the entire back surface on the opposite side (in many cases, devices that handle high-speed signals have a back electrode formed on the entire back surface). When mounting using the tape carrier 13, conventionally, first ILB is performed and then OLB
I do.
ＩＬＢ工程では、ボンダーのワーク載せ台１５に半導体
素子１１を位置決め載置する。テープキャリア１３のリ
ード１３ｂのインナーリード１３ｂ−１（金めつきが施
されている）に別工程で金バンプ１７．を付着し、その
インナーリードｔ３ｂ−ｔを位置決めした半導体素子１
１の表面電極１１ａ−１上に位置合わせ近接させ、ボン
ダーの熱圧着ヘンダ１６ａを矢印方向に降下して加圧・
加熱し熱圧着を行う。In the ILB process, the semiconductor element 11 is positioned and mounted on the workpiece mounting table 15 of the bonder. Gold bumps 17. are applied to the inner leads 13b-1 (gold plated) of the leads 13b of the tape carrier 13 in a separate process. semiconductor element 1 to which the inner leads t3b-t are positioned
The thermocompression bonding helder 16a of the bonder is lowered in the direction of the arrow to apply pressure.
Heat and perform thermocompression bonding.
つぎに、第４図の要部側断面図に示すように別工程でア
ウターリード１３ｂ−２をテープフィルム１３ａからパ
ンチング加工により所定形状に切断、整形する。一方、
回路基板１２の配線ランド１２ａ−２面上に銀エポキシ
系の熱硬化性・導電性接着剤１８を塗布する。Next, as shown in the sectional side view of the main part in FIG. 4, in a separate process, the outer lead 13b-2 is cut and shaped into a predetermined shape from the tape film 13a by punching. on the other hand,
A silver epoxy thermosetting/conductive adhesive 18 is applied onto the wiring land 12a-2 surface of the circuit board 12.
そして、半導体素子１１をフェイスアップにし、錫−鉛
系の低融点の半田コーテイング膜１９を予め被着した回
路基板１２の配線ランド１２ａ−１にアウターリード１
３ｂ−２を位置合わせして載せＩＬＢ時と同様にボンダ
ーの熱圧着ヘッダ１６ｂを矢印方向に降下させて加圧・
加熱しＯＬＢを行うとともに、ダイｌ１ａ真面の裏面電
極１１ａ−２面を回路基板１２の配線ランド１２ａ−２
の予め塗布した熱硬化性・導電性接着剤１８に圧着する
。その後、回路基板１２全体を加熱しこの接着剤１８を
熱硬化している。Then, with the semiconductor element 11 facing up, the outer lead 1 is attached to the wiring land 12a-1 of the circuit board 12 on which a tin-lead based low melting point solder coating film 19 has been previously coated.
3b-2 is aligned and placed, as in the case of ILB, the thermocompression header 16b of the bonder is lowered in the direction of the arrow to apply pressure.
While heating and performing OLB, the back electrode 11a-2 surface directly in front of the die l1a is connected to the wiring land 12a-2 of the circuit board 12.
The thermosetting/conductive adhesive 18 is applied in advance. Thereafter, the entire circuit board 12 is heated to thermoset the adhesive 18.
しかしながら、このような上記方法によれば、特にＩＬ
Ｂ工程において、熱圧着ヘッダの加圧力による衝撃など
により半導体素子が時に機械的に破壊されるという問題
があり、また実装された半導体素子の中に不良が発見さ
れた場合、アウターリードは錫−鉛系の低融点半田で接
合されているためアウターリードだけを部分的に加熱溶
融して容易に外すことができるが、半導体素子のダイは
熱硬化性接着剤で固着されているため容易に外すことが
できずその半導体素子を破壊したり、あるいは他の半導
体素子や回路基板の基材を損傷するといった問題があっ
た。However, according to the above method, especially IL
In the B process, there is a problem that the semiconductor element is sometimes mechanically destroyed due to the impact caused by the pressurizing force of the thermocompression header, and if a defect is found in the mounted semiconductor element, the outer lead is Since they are joined with lead-based low melting point solder, only the outer leads can be easily removed by partially heating and melting them, but the semiconductor element die is fixed with a thermosetting adhesive and can be easily removed. There was a problem that the semiconductor element could not be removed and the semiconductor element could be destroyed, or other semiconductor elements or the base material of the circuit board could be damaged.
上記問題点に鑑み、本発明は半導体素子のテープキャリ
アによるボンディング時の加圧力による衝撃を緩衝し機
械的破壊を減少することと、回路基板に固着された不良
の半導体素子を外し易くする半導体素子の実装方法を提
供することを目的とする。In view of the above-mentioned problems, the present invention provides a semiconductor element that reduces mechanical damage by reducing the impact caused by the pressing force during bonding of semiconductor elements with a tape carrier, and that makes it easier to remove defective semiconductor elements stuck to a circuit board. The purpose is to provide an implementation method.
上記目的を達成するために、本発明の半導体素子の実装
方法においては、ダイの裏面全面に導電性ポリマー膜を
予め形成した後、前記表面電極にテープキャリアをイン
ナーリードボンディングする工程と、前記回路基板の配
線ランドを含む前記ダイ裏面全面との対向面上に導電性
ポリマー膜を予め形成し、さらにその上に導電性接着剤
を塗布した後、テープキャリアを用いてインナーリード
ボンディングされた半導体素子を配線ランドにフェイス
アップでアウターリードボンディングするとともに、ダ
イを前記接着剤で固着する工程との両工程を含むか、あ
るいはどちらか一方の工程を含むように槽底する。In order to achieve the above object, the semiconductor device mounting method of the present invention includes the steps of forming a conductive polymer film on the entire back surface of the die in advance, and then bonding a tape carrier to the surface electrode with inner leads; A semiconductor element in which a conductive polymer film is formed in advance on the surface facing the entire back surface of the die including the wiring land of the substrate, and a conductive adhesive is further applied thereon, and then inner lead bonding is performed using a tape carrier. The bottom of the tank is designed to include both the steps of face-up outer lead bonding to the wiring land and the step of fixing the die with the adhesive, or either one of the steps.
半導体素子のダイの裏面電極面に導電性ポリマー膜を予
め形成しておくことにより、ＩＬＢ時の加圧力による衝
撃を緩衝することができて半導体素子の機械的破壊を減
少することができる。By forming a conductive polymer film in advance on the back electrode surface of the die of the semiconductor element, it is possible to buffer the impact caused by the pressure during ILB and reduce mechanical damage to the semiconductor element.
また、不良の半導体素子がＯＬＢ及びダイボンディング
後に見つかれば、この導電性ポリマー膜位置で容易に剥
がすことができ取り替えがし易くなる。Moreover, if a defective semiconductor element is found after OLB and die bonding, it can be easily peeled off at this conductive polymer film position, making it easier to replace it.
以下図面に示した実施例に基づいて本発明の要旨を詳細
に説明する。The gist of the present invention will be explained in detail below based on embodiments shown in the drawings.
第１図の側断面図に示すように、ダイ１ａの表面に表面
電極１ａ−１（信号用あるいは電源用電極）を、その反
対裏面全面に裏面電極１ａ−２（接地用電極あるいは電
源用電極）を備える。（高速信号を扱う素子は裏面全面
に裏面電極を形成している場合が多い）
半導体素子１を回路基板２にテープキャリア３を用いて
実装する場合、ＩＬＢに先立ち半導体素子１のダイ１ａ
裏面全面、即ち裏面電極１ａ−２面に導電性ポリマー膜
４、即ちＡ−１、例えばポリアセチレン膜あるいはポリ
ピロール膜を形成しイオン注入や気相拡散などの技術を
用いてドーピングし高１ｌｔｔ性化しておく。As shown in the side cross-sectional view of FIG. ). (Elements that handle high-speed signals often have a back electrode formed on the entire back surface.) When mounting the semiconductor element 1 on the circuit board 2 using the tape carrier 3, the die 1a of the semiconductor element 1 is mounted before ILB.
A conductive polymer film 4, ie, A-1, for example, a polyacetylene film or a polypyrrole film, is formed on the entire back surface, that is, on the back electrode 1a-2 surface, and is doped using techniques such as ion implantation and vapor phase diffusion to make it highly 1ltt. put.
そうして、ＩＬＢ工程ではボンダーのワーク載せ台５に
予め、導電性ポリマー膜４−１を形成した上記半導体素
子１を位置決め載置する。テープキャリア３のリード３
ｂのインナーリード３ｂ−１（金めつきが施されている
）に別工程で金バンプ７を付着し、そのインナーリード
３ｂ−１を位置決めした半導体素子１に位置合わせ近接
させ、ボンダーの熱圧着ヘッダ６ａを矢印方向に降下し
て加圧・加熱し熱圧着を行う。Then, in the ILB process, the semiconductor element 1 on which the conductive polymer film 4-1 has been formed is positioned and mounted on the workpiece mounting table 5 of the bonder. Lead 3 of tape carrier 3
A gold bump 7 is attached to the inner lead 3b-1 (gold plated) of b in a separate process, and the inner lead 3b-1 is aligned and brought close to the positioned semiconductor element 1, and bonded by thermocompression with a bonder. The header 6a is lowered in the direction of the arrow and pressurized and heated to perform thermocompression bonding.
つぎに、第２図の側断面図に示すように別工程でテープ
キャリア３のアウターリード３ｂ−２をテープフィルム
３ａからパンチング加工により所定形状に切断、整形す
る。一方、半導体素子ｌの裏面電極１ａ−２を接着する
回路基板２の配線ランド２ａ−２面にも導電性ポリマー
膜（ポリアセチレン膜）４、即ち４−２を形成した後、
ドーピングし高導電性化しておく、（もし、裏面電極１
ａ−２がダイ１ａ裏面全面に無＜−１部に形成されてい
る場合は回路基板２のダイ１８８面全面との配線ランド
２ａ−２を含む対向面に導電性ポリマー膜４−２を形成
する〉そして、その導電性ポリマー膜４−２上に銀エポ
キシ系の熱硬化性・導電性接着剤８を塗布する。Next, as shown in the side sectional view of FIG. 2, in a separate process, the outer leads 3b-2 of the tape carrier 3 are cut and shaped into a predetermined shape from the tape film 3a by punching. On the other hand, after forming a conductive polymer film (polyacetylene film) 4, that is, 4-2 on the wiring land 2a-2 surface of the circuit board 2 to which the back electrode 1a-2 of the semiconductor element 1 is bonded,
Make it highly conductive by doping (if the back electrode 1
If a-2 is formed on the entire back surface of the die 1a in a non-<-1 part, a conductive polymer film 4-2 is formed on the opposite surface including the wiring land 2a-2 and the entire surface of the die 188 of the circuit board 2. Then, a silver epoxy thermosetting/conductive adhesive 8 is applied onto the conductive polymer film 4-2.
その際、接着剤８が熱硬化後に導電性ポリマー膜４−２
からはみ出すと、接着剤８が直接、回路基板２に固着し
てダイ１ａが剥がしにくくなるためはみ出さないように
塗布する。At that time, after the adhesive 8 is thermally cured, the conductive polymer film 4-2
If it protrudes, the adhesive 8 will directly adhere to the circuit board 2, making it difficult to remove the die 1a, so apply it so that it does not protrude.
つぎに、ＩＬＢされた半導体素子１をフェイスアップに
し、錫−鉛系の低融点の半田コーテイング膜９を被着し
た配線ランド２ａ−１にアウターリード３ｂを位置合わ
せして回路基板２に載せ、ＩＬＢ時と同様にボングーの
熱圧着ヘッダ６ｂを矢印方向に降下させて加圧・加熱し
ＯＬＢを行うとともに、ダイ１ａ裏面の裏面電極１ａ−
２面を回路基板２の配線ランド２ａ−２の予め塗布した
前記接着剤８に圧着する。その後、回路基板２全体を加
熱しこの接着剤８を熱硬化してダイ１ａを固着し実装を
完了する。Next, the ILBed semiconductor element 1 is placed face up, the outer leads 3b are aligned with the wiring lands 2a-1 covered with a tin-lead based low melting point solder coating film 9, and placed on the circuit board 2. As in ILB, the thermocompression bonding header 6b of the bongoo is lowered in the direction of the arrow, pressurized and heated to perform OLB, and the back electrode 1a- on the back surface of the die 1a.
The two sides are pressure-bonded to the adhesive 8 applied in advance on the wiring land 2a-2 of the circuit board 2. Thereafter, the entire circuit board 2 is heated and the adhesive 8 is thermally cured to fix the die 1a and complete the mounting.
もし、ボンディング後の回路動作試験で半導体素子の特
性不良あるいは接合不良などが見つかれば、アウターリ
ードを接合した半田を加熱溶融して外すとともにダイを
導電性ポリマー膜位置で引き剥がして半導体素子を良品
に取り替え、上記と同様の工程でボンディングを行い再
実装する。If a defect in the characteristics of the semiconductor element or a defective connection is found in the circuit operation test after bonding, the solder that connected the outer lead is removed by heating and melted, and the die is peeled off at the conductive polymer film position to make the semiconductor element good. Replace it with , perform bonding and remount using the same process as above.
このように、半導体素子と回路基板との間の半導体素子
側に導電性ポリマー膜を予め、形成しておきＩＬＢを行
うことにより、ＩＬＢ時の加圧力による衝撃を吸収する
ことができ、半導体素子の機械的破壊を減少することが
できる。In this way, by forming a conductive polymer film in advance on the semiconductor element side between the semiconductor element and the circuit board and performing ILB, it is possible to absorb the impact caused by the pressurizing force during ILB, and the semiconductor element Mechanical damage can be reduced.
また、導電性ポリマー膜はある程度の力できれい引き剥
がすことができるため、半導体素子の取り替えを容易に
行うことができる。Furthermore, since the conductive polymer film can be peeled off cleanly with a certain amount of force, the semiconductor element can be easily replaced.
なお、上記説明した導電性ポリマー膜は半導体素子側と
回路基板側双方に形成したが、とくにインナーリードボ
ンディング時の加圧力の衝撃を吸収する意味で半導体素
子側にだけ形成してもよく、同様に半導体素子を容易に
ひき剥がすことができることは言うまでもない。Although the conductive polymer film explained above is formed on both the semiconductor element side and the circuit board side, it may also be formed only on the semiconductor element side, especially in order to absorb the impact of the pressurizing force during inner lead bonding. Needless to say, the semiconductor element can be easily peeled off.
以上、詳述したように本発明によれば、ＩＬＢ時の加圧
力による衝撃を吸収して半導体素子の機械的破壊を減少
するとともに、不良半導体素子の取り替えを容易に行う
ことができ、電子回路の信頼性の向上と手直しの時間短
縮ができて作業効率の向上を図ることができるといった
産業上極めて有用な効果を発揮する。As described in detail above, according to the present invention, it is possible to absorb the impact caused by the pressure during ILB and reduce mechanical damage to semiconductor elements, and also to easily replace defective semiconductor elements, and to It has extremely useful effects in industry, such as improving reliability and shortening the time for rework, thereby improving work efficiency.
第１図は本発明による一実施例のＩＬＢの状態を示す要
部側断面図、
第２図は第１図のＩＬＢ後、ＯＬＢの状態を示す要部側
断面図、
第３図は従来技術によるＩＬＢの状態を示す要部側断面
図、
第４図は第３図のＩＬＢ後、ＯＬＢの状態を示す要部側
断面図である。
図において、
１は半導体素子、
１ａはダイ、
１ａ−１は表面電極、
１ａ−２は裏面電極、
２は回路基板、
２ａ−１，２ａ−２は配線ランド、
３はテープキャリア、
４は導電性ポリマー膜（ポリアセチレン膜）８は導電性
接着剤を示す。FIG. 1 is a side sectional view of the main part showing the state of the ILB in an embodiment of the present invention, FIG. 2 is a side sectional view of the main part showing the state of the OLB after the ILB in FIG. 1, and FIG. 3 is the prior art. FIG. 4 is a side sectional view of the main part showing the state of the OLB after the ILB shown in FIG. 3. FIG. In the figure, 1 is a semiconductor element, 1a is a die, 1a-1 is a front electrode, 1a-2 is a back electrode, 2 is a circuit board, 2a-1 and 2a-2 are wiring lands, 3 is a tape carrier, and 4 is a conductor. A conductive polymer film (polyacetylene film) 8 represents a conductive adhesive.
Claims (1)
対裏面に裏面電極（１ａ−２）を備える半導体素子（１
）を回路基板（２）上に実装する工程中において、前記
ダイ（１ａ）の裏面全面に導電性ポリマー膜（４−１）
を予め形成した後、前記表面電極（１ａ−１）にテープ
キャリア（３）をインナーリードボンディングする工程
と、 前記回路基板（２）の配線ランド（２ａ−２）を含む前
記ダイ（１ａ）裏面全面との対向面上に導電性ポリマー
膜（４−２）を予め形成し、さらにその上に導電性接着
剤（８）を塗布した後、テープキャリア（３）を用いて
インナーリードボンディングされた半導体素子（１）を
配線ランド（２ａ−１）にフェイスアップでアウターリ
ードボンディングするとともに、ダイ（１ａ）を前記接
着剤（８）で固着する工程との両工程を含むか、あるい
はどちらか一方の工程を含むことを特徴とする半導体素
子の実装方法。[Claims] A semiconductor element (1) comprising a front electrode (1a-1) on the front surface of a die (1a) and a back electrode (1a-2) on the opposite back surface.
) on the circuit board (2), a conductive polymer film (4-1) is applied to the entire back surface of the die (1a).
a step of bonding a tape carrier (3) to the surface electrode (1a-1) by inner lead after forming the surface electrode (1a-1) in advance; A conductive polymer film (4-2) was previously formed on the surface facing the entire surface, and a conductive adhesive (8) was further applied thereon, followed by inner lead bonding using a tape carrier (3). Includes both the steps of face-up outer lead bonding of the semiconductor element (1) to the wiring land (2a-1) and the step of fixing the die (1a) with the adhesive (8), or either one of them. A method for mounting a semiconductor device, comprising the steps of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1218083A JPH0380549A (en) | 1989-08-23 | 1989-08-23 | Mounting of semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1218083A JPH0380549A (en) | 1989-08-23 | 1989-08-23 | Mounting of semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0380549A true JPH0380549A (en) | 1991-04-05 |
Family
ID=16714373
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1218083A Pending JPH0380549A (en) | 1989-08-23 | 1989-08-23 | Mounting of semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0380549A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01281183A (en) * | 1988-05-02 | 1989-11-13 | Tiger Kawashima Co Ltd | Vertical grain sorter |
| WO2001015216A1 (en) * | 1999-08-25 | 2001-03-01 | Hitachi, Ltd. | Semiconductor device and method of manufacture thereof |
-
1989
- 1989-08-23 JP JP1218083A patent/JPH0380549A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01281183A (en) * | 1988-05-02 | 1989-11-13 | Tiger Kawashima Co Ltd | Vertical grain sorter |
| WO2001015216A1 (en) * | 1999-08-25 | 2001-03-01 | Hitachi, Ltd. | Semiconductor device and method of manufacture thereof |
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