JP2000101013A - Method of mounting mixed components including bare chip component, and mixed circuit board - Google Patents
Method of mounting mixed components including bare chip component, and mixed circuit boardInfo
- Publication number
- JP2000101013A JP2000101013A JP26436698A JP26436698A JP2000101013A JP 2000101013 A JP2000101013 A JP 2000101013A JP 26436698 A JP26436698 A JP 26436698A JP 26436698 A JP26436698 A JP 26436698A JP 2000101013 A JP2000101013 A JP 2000101013A
- Authority
- JP
- Japan
- Prior art keywords
- bare chip
- substrate
- mounting
- solder
- adhesive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/75252—Means for applying energy, e.g. heating means in the upper part of the bonding apparatus, e.g. in the bonding head
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、同一基板上にベア
チップを含む複数の部品を実装してなる混載回路基板お
よびベアチップを含む混載部品の実装方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mixed circuit board having a plurality of components including a bare chip mounted on the same substrate and a method of mounting a mixed component including a bare chip.
【０００２】[0002]
【従来の技術】基板上にベアチップを実装する方法の１
つにベアチップの端子にバンプを形成し、このバンプを
基板のベアチップ接合部に接合する方法がある。具体的
には、まず、半田をプリコートしたベアチップ接合部に
熱硬化性のゲル状の接着シートを貼付し、この接着シー
トの上からベアチップを押下してバンプを半田に接触さ
せた状態で加熱することにより、ベアチップがベアチッ
プ接合部に固着させるというものである。2. Description of the Related Art One of the methods for mounting a bare chip on a substrate is as follows.
Finally, there is a method in which a bump is formed on a terminal of a bare chip and the bump is bonded to a bare chip bonding portion of the substrate. Specifically, first, a thermosetting gel-like adhesive sheet is attached to the bare chip bonding portion pre-coated with solder, and the bare chip is pressed down from above the adhesive sheet and heated while the bumps are in contact with the solder. Thus, the bare chip is fixed to the bare chip joint.
【０００３】[0003]
【発明が解決しようとする課題】ところで、近年の電子
機器の小型化により、機器内部の基板の小型化も重要な
課題になっており、そのためにベアチップと他の部品を
同一基板上に実装できる技術が要求されている。しか
し、ベアチップと他の部品を同一基板上にマウント・リ
フローによって同時に実装することは、ベアチップの端
子のピッチの細かさ等の理由により困難である。By the way, with the recent miniaturization of electronic equipment, miniaturization of the substrate inside the equipment has become an important issue, so that a bare chip and other components can be mounted on the same substrate. Technology is required. However, it is difficult to simultaneously mount the bare chip and other components on the same substrate by mount reflow because of the fine pitch of the terminals of the bare chip.
【０００４】そこで、ベアチップの実装工程と他の部品
の実装工程とを分けて行うことが考えられるが、この場
合２つの方法が考えられる。１つは、他の部品を基板上
にマウント・リフローによって実装した後にベアチップ
を実装する方法であり、もう１つは、ベアチップを実装
したのちに他の部品を実装する方法である。前者の場合
は、フラックス等によるベアチップ接合部の汚染や、プ
リコートした半田の酸化によりベアチップの接続不良を
招くおそれがある。そのため、後者の方法で実装する方
がベアチップに与える影響が少なくてすむ。[0004] Therefore, it is conceivable that the step of mounting a bare chip and the step of mounting other components are performed separately. In this case, two methods are conceivable. One is a method of mounting a bare chip after mounting another component on a substrate by mount reflow, and the other is a method of mounting another component after mounting the bare chip. In the former case, there is a possibility that contamination of the bare chip joint portion due to the flux or the like or oxidation of the precoated solder may cause poor connection of the bare chip. For this reason, mounting by the latter method has less influence on the bare chip.
【０００５】しかし、後者の場合においても、マウント
・リフローによってベアチップと基板との間の半田が溶
融するが半田の周囲の接着シートは膨張しないために、
ベアチップが基板から剥離したり、破壊されるおそれが
ある。However, even in the latter case, the solder between the bare chip and the substrate is melted by the mount reflow, but the adhesive sheet around the solder does not expand.
The bare chip may be peeled off from the substrate or broken.
【０００６】本発明は、後者の場合における問題点を解
決するものであり、ベアチップと他の部品とを同一基板
上にマウント・リフローによって実装する際に、基板か
らベアチップが剥離することやベアチップが破壊される
ことを防止した混載回路基板およびベアチップを含む混
載部品の実装方法に関する。The present invention solves the problem in the latter case. When a bare chip and another component are mounted on the same substrate by mount reflow, the bare chip may be peeled off from the substrate or the bare chip may be removed. The present invention relates to an embedded circuit board and a mounting method of an embedded component including a bare chip which are prevented from being broken.
【０００７】[0007]
【課題を解決するための手段】前記目的を達成するため
の本発明は、ベアチップおよび他の部品を同一基板上に
実装する混載部品の実装方法において、基板上における
ベアチップの端子に接合するベアチップ接合部および他
の部品の端子に接合する部品接合部に半田を供給する工
程と、前記ベアチップ接合部に半田溶融温度で軟化状態
となる接着部材を供給する工程と、ベアチップを加圧し
かつ前記接着部材を加熱してベアチップの端子と前記ベ
アチップ接合部とを半田によって接合する工程と、前記
部品接合部にフラックスを塗布して他の部品を載置して
マウント・リフロー方式により他の部品の端子と前記部
品接合部とを接合する工程とを有することを特徴とす
る。このような方法により、マウント・リフロー時に、
ベアチップ接合部の半田の膨張および収縮に追随して接
着部材が拡張および縮小するようになるため、ベアチッ
プの接合剥離や破壊を防止することができる。SUMMARY OF THE INVENTION In order to achieve the above object, the present invention relates to a method of mounting a bare chip and other parts on a same substrate, and a method of mounting bare chips to terminals of bare chips on a substrate. Supplying solder to a component joining portion to be joined to a terminal of a component and another component, supplying an adhesive member which becomes a softened state at a solder melting temperature to the bare chip joining portion, pressing a bare chip and applying the adhesive member Heating the bare chip terminal and the bare chip bonding portion by soldering, and applying a flux to the component bonding portion, mounting another component, and mounting and reflowing a terminal of another component. And joining the component joining portion. In this way, during mount reflow,
Since the adhesive member expands and contracts following the expansion and contraction of the solder at the bare chip joint, the peeling and destruction of the bare chip can be prevented.
【０００８】また本発明は、ベアチップの端子に接合す
るベアチップ接合部と他の部品の端子に接合する部品接
合部とを有する基板に、ベアチップおよび他の部品を半
田付けによって実装してなる実装基板において、半田に
よって接続されている前記ベアチップの端子とベアチッ
プ接合部との間を、半田溶融温度で軟化状態となる接着
部材で封止したことを特徴とする。このような構成によ
り、ベアチップ接合部の半田の膨張および収縮に追随し
て接着部材が拡張および縮小するようになるため、ベア
チップを搭載した基板に対して他の部品をマウント・リ
フローによって半田付けをすることが可能になり、作業
コストの削減が図れる。Further, the present invention provides a mounting board formed by mounting a bare chip and other components by soldering on a substrate having a bare chip bonding portion bonded to a bare chip terminal and a component bonding portion bonded to a terminal of another component. Wherein the space between the bare chip terminal and the bare chip joint, which are connected by solder, is sealed with an adhesive member that becomes soft at the solder melting temperature. With such a configuration, the adhesive member expands and contracts in accordance with the expansion and contraction of the solder at the bare chip joint, so that other components can be soldered to the board on which the bare chip is mounted by mounting and reflowing. Work cost can be reduced.
【０００９】[0009]
【発明の実施の形態】以下、本発明の実施形態につい
て、図面を参照して詳細に説明する。Embodiments of the present invention will be described below in detail with reference to the drawings.
【００１０】図１は本発明のベアチップ部品を含む混載
部品の実装方法の実施形態における実装工程を示す工程
図であり、１は基板、２は基板１の電極パッド、３は半
田、４は接着剤、５はベアチップ、６はベアチップ５の
電極、７は電極６に形成されたバンプ、８は基板１を載
置するステージ、９はベアチップ５を基板１側に押下し
ながら加熱する加圧・加熱ツール、１０は混載部品、１
１は混載部品１０の電極を示す。FIG. 1 is a process diagram showing a mounting process in an embodiment of a method of mounting a mixed component including a bare chip component according to the present invention, wherein 1 is a substrate, 2 is an electrode pad of the substrate 1, 3 is a solder, and 4 is an adhesive. The agent 5 is a bare chip, 6 is an electrode of the bare chip 5, 7 is a bump formed on the electrode 6, 8 is a stage on which the substrate 1 is mounted, and 9 is a pressurizing / heating device that presses the bare chip 5 toward the substrate 1 while heating. Heating tool, 10 for mixed components, 1
Reference numeral 1 denotes an electrode of the mixed component 10.
【００１１】まず、図１（ａ）に示すように、基板１に
おける電極パッド２に半田３をプリコートする。次に、
図１（ｂ）に示すように、基板１におけるベアチップ５
を実装する電極パッド２の部位に接着剤４を供給する。
この接着剤４は、半田溶融温度前後の温度域で軟化する
特性を有する材質であり、例えば、ポリエステル，ポリ
ビニルアセタール，アクリル，ポリイミド，セルロース
アセテート等の熱可塑性接着材あるいは変性アクリレー
ト樹脂等の紫外線硬化接着材を用いることができる。ま
た、接着剤４としては、ゲル状のシート材として電極パ
ッド２の部位に貼付されるか、あるいは高い粘性を有す
る液体の状態で塗布される。First, as shown in FIG. 1A, a solder 3 is pre-coated on an electrode pad 2 on a substrate 1. next,
As shown in FIG. 1B, the bare chip 5 on the substrate 1
Is supplied to the portion of the electrode pad 2 on which is mounted.
The adhesive 4 is a material having a property of softening in a temperature range around the solder melting temperature, and is, for example, a thermoplastic adhesive such as polyester, polyvinyl acetal, acryl, polyimide, or cellulose acetate, or an ultraviolet curable material such as a modified acrylate resin. An adhesive can be used. The adhesive 4 is applied to the electrode pad 2 as a gel-like sheet material or is applied in a state of a liquid having high viscosity.
【００１２】次に、基板１をステージ８に載置し、加圧
・加熱ツール９にベアチップ５を保持させ、ベアチップ
５を基板１側に押下しながらバンプ７を半田３に当接さ
せた状態で加熱することにより、図１（ｃ）に示すよう
に、ベアチップ５を基板１に実装する。Next, the substrate 1 is placed on the stage 8, the bare chip 5 is held by the pressurizing / heating tool 9, and the bump 7 is brought into contact with the solder 3 while the bare chip 5 is pressed down to the substrate 1 side. The bare chip 5 is mounted on the substrate 1 as shown in FIG.
【００１３】次に、基板１における混載部品１０を実装
する電極パッド２の部位に粘着性の高いフラックスを塗
布し、図１（ｄ）に示すように、混載部品１０の電極１
１を対応する電極パッド２に載置する。そして、マウン
ト・リフローにより基板１を加熱することにより、図１
（ｅ）に示すように、混載部品１０が基板１上に実装さ
れ、混載回路基板の作成が完了する。Next, a highly adhesive flux is applied to a portion of the substrate 1 where the electrode pad 2 for mounting the mixed component 10 is mounted, and as shown in FIG.
1 is placed on the corresponding electrode pad 2. Then, by heating the substrate 1 by mount reflow, FIG.
As shown in (e), the hybrid component 10 is mounted on the board 1, and the creation of the hybrid circuit board is completed.
【００１４】図２はマウント・リフロー時におけるベア
チップと基板との接合状態を示す説明図である。FIG. 2 is an explanatory view showing a bonding state between a bare chip and a substrate during mount reflow.
【００１５】マウント・リフロー前は図２（ａ）に示す
ように、半田３の周囲で接着剤４が硬化した状態にあ
る。マウント・リフロー中は、図２（ｂ）に示すよう
に、半田３が接着剤４の内部で溶融して体積膨張する。
この時、接着剤４は、半田溶融温度前後の温度域で（１
７０〜２３０℃）ゲル状または高い柔軟性を持つように
なるため、半田３の体積膨張に追従して、接着剤４にお
ける半田３の周囲の部分が拡張する。マウント・リフロ
ー後は、図２（ｃ）に示すように、基板１は冷却され、
半田３は硬化しながら体積が減少して元の状態に戻る。
この時、半田３の体積減少に伴って、接着剤４における
半田３の周囲の部分が縮小する。Before the mounting reflow, as shown in FIG. 2A, the adhesive 4 is in a state of being hardened around the solder 3. During mount reflow, as shown in FIG. 2B, the solder 3 melts inside the adhesive 4 and expands in volume.
At this time, the adhesive 4 has a temperature (1) in a temperature range around the solder melting temperature.
(70 ° C. to 230 ° C.) Since it becomes gel-like or has high flexibility, the portion of the adhesive 4 around the solder 3 expands following the volume expansion of the solder 3. After the mount reflow, the substrate 1 is cooled as shown in FIG.
The volume of the solder 3 decreases as it hardens, and returns to its original state.
At this time, as the volume of the solder 3 is reduced, a portion of the adhesive 4 around the solder 3 is reduced.
【００１６】このように本実施形態によれば、マウント
リフロー時における接着剤４の内部の半田３の体積膨張
および収縮に追従して、接着剤４における半田３の周囲
の部分が拡張および縮小するため、半田接合によるベア
チップ実装の後に他の部品をリフローにより実装するこ
とができる。As described above, according to the present embodiment, the portion of the adhesive 4 around the solder 3 expands and contracts following the volume expansion and contraction of the solder 3 inside the adhesive 4 during mount reflow. Therefore, other components can be mounted by reflow after bare chip mounting by soldering.
【００１７】なお、本実施形態においては、エポキシの
ような熱硬化性接着剤であっても、半田溶融温度で樹脂
が軟化し、半田の体積変化に追従できるものであれば適
用可能である。In this embodiment, a thermosetting adhesive such as epoxy can be applied as long as the resin softens at the solder melting temperature and can follow the change in the volume of the solder.
【００１８】[0018]
【発明の効果】本発明によれば、ベアチップと基板との
接着部材が熱軟化性を有するため、マウントリフロー時
における接着部材の内部の半田の体積膨張および収縮に
追従して、接着部材における半田の周囲の部分が拡張お
よび縮小するため、半田接合によるベアチップ実装の後
に他の部品をリフローにより実装することができる。According to the present invention, since the bonding member between the bare chip and the substrate has thermal softening properties, the solder in the bonding member follows the volume expansion and contraction of the solder inside the bonding member during mount reflow. Since the surrounding portion expands and contracts, other components can be mounted by reflow after bare chip mounting by soldering.
【図１】本発明のベアチップ部品を含む混載部品の実装
方法の実施形態における実装工程を示す工程図FIG. 1 is a process diagram showing a mounting process in an embodiment of a method of mounting mixed components including bare chip components according to the present invention.
【図２】マウント・リフロー時におけるベアチップと基
板との接合状態を示す説明図FIG. 2 is an explanatory view showing a bonding state between a bare chip and a substrate at the time of mount reflow;
１ 基板 ２ 電極パッド ３ 半田 ４ 接着剤 ５ ベアチップ ６，１１ 電極 ７ バンプ ８ ステージ ９ 加圧・加熱ツール １０ 混載部品 DESCRIPTION OF SYMBOLS 1 Substrate 2 Electrode pad 3 Solder 4 Adhesive 5 Bare chip 6, 11 Electrode 7 Bump 8 Stage 9 Pressurization / heating tool 10 Mixed components
Claims (2)
に実装する混載部品の実装方法において、 基板上におけるベアチップの端子に接合するベアチップ
接合部および他の部品の端子に接合する部品接合部に半
田を供給する工程と、前記ベアチップ接合部に半田溶融
温度で軟化状態となる接着部材を供給する工程と、ベア
チップを加圧しかつ前記接着部材を加熱してベアチップ
の端子と前記ベアチップ接合部とを半田によって接合す
る工程と、前記部品接合部にフラックスを塗布して他の
部品を載置してマウント・リフロー方式により他の部品
の端子と前記部品接合部とを接合する工程とを有するこ
とを特徴とするベアチップ部品を含む混載部品の実装方
法。1. A method of mounting a bare chip and another component on the same substrate, the method comprising: mounting a bare chip joint to a bare chip terminal on a substrate and a component joint to a terminal of another component on a substrate. Supplying the adhesive member to be softened at the solder melting temperature to the bare chip bonding portion, and pressing the bare chip and heating the bonding member to solder the bare chip terminal and the bare chip bonding portion. And a step of applying a flux to the component joint, mounting another component, and joining a terminal of the other component and the component joint by a mount reflow method. Of mounting mixed components including bare chip components.
接合部と他の部品の端子に接合する部品接合部とを有す
る基板に、ベアチップおよび他の部品を半田付けによっ
て実装してなる混載回路基板において、 半田によって接続されている前記ベアチップの端子とベ
アチップ接合部との間を、半田溶融温度で軟化状態とな
る接着部材で封止したことを特徴とする混載回路基板。2. A mixed circuit board comprising a bare chip and other components mounted on a substrate having a bare chip bonding portion bonded to terminals of bare chips and a component bonding portion bonded to terminals of other components by soldering. A mixed circuit board, wherein a space between a terminal of the bare chip connected by solder and a bare chip joining portion is sealed with an adhesive member which is softened at a solder melting temperature.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26436698A JP2000101013A (en) | 1998-09-18 | 1998-09-18 | Method of mounting mixed components including bare chip component, and mixed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26436698A JP2000101013A (en) | 1998-09-18 | 1998-09-18 | Method of mounting mixed components including bare chip component, and mixed circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000101013A true JP2000101013A (en) | 2000-04-07 |
Family
ID=17402165
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26436698A Pending JP2000101013A (en) | 1998-09-18 | 1998-09-18 | Method of mounting mixed components including bare chip component, and mixed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000101013A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003017979A (en) * | 2001-06-28 | 2003-01-17 | Nagase Chemtex Corp | Surface acoustic wave device and its manufacturing method |
| WO2004003993A1 (en) * | 2002-07-01 | 2004-01-08 | Toray Engineering Co., Ltd. | Packaging method and packaging system |
| CN102695373A (en) * | 2011-03-25 | 2012-09-26 | 株式会社日立工业设备技术 | Printed substrate manufacturing equipment and manufacturing method |
| KR101210586B1 (en) * | 2011-04-20 | 2012-12-11 | 한국생산기술연구원 | Flip Chip Package Using Adhesive Containing Volume Expansion Additives and Its Joining Method |
| CN113056113A (en) * | 2020-07-31 | 2021-06-29 | 广州立景创新科技有限公司 | Method for manufacturing electronic component module |
-
1998
- 1998-09-18 JP JP26436698A patent/JP2000101013A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003017979A (en) * | 2001-06-28 | 2003-01-17 | Nagase Chemtex Corp | Surface acoustic wave device and its manufacturing method |
| WO2004003993A1 (en) * | 2002-07-01 | 2004-01-08 | Toray Engineering Co., Ltd. | Packaging method and packaging system |
| CN102695373A (en) * | 2011-03-25 | 2012-09-26 | 株式会社日立工业设备技术 | Printed substrate manufacturing equipment and manufacturing method |
| CN102695373B (en) * | 2011-03-25 | 2015-01-28 | 株式会社日立制作所 | Printed substrate manufacturing equipment and manufacturing method |
| KR101210586B1 (en) * | 2011-04-20 | 2012-12-11 | 한국생산기술연구원 | Flip Chip Package Using Adhesive Containing Volume Expansion Additives and Its Joining Method |
| CN113056113A (en) * | 2020-07-31 | 2021-06-29 | 广州立景创新科技有限公司 | Method for manufacturing electronic component module |
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