JPH0378834A - Data processing system - Google Patents

Data processing system

Info

Publication number
JPH0378834A
JPH0378834A JP21622489A JP21622489A JPH0378834A JP H0378834 A JPH0378834 A JP H0378834A JP 21622489 A JP21622489 A JP 21622489A JP 21622489 A JP21622489 A JP 21622489A JP H0378834 A JPH0378834 A JP H0378834A
Authority
JP
Japan
Prior art keywords
registers
instruction
saved
data processing
high function
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21622489A
Other languages
Japanese (ja)
Inventor
Etsuko Ota
太田 悦子
Hiroki Takita
浩樹 瀧田
Toru Shimizu
徹 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP21622489A priority Critical patent/JPH0378834A/en
Publication of JPH0378834A publication Critical patent/JPH0378834A/en
Pending legal-status Critical Current

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  • Devices For Executing Special Programs (AREA)

Abstract

PURPOSE:To maximize the executing speed in a data processing system by selecting the output of a high function instruction or a basic instruction according to the output conditions of the high function instruction. CONSTITUTION:An instruction which carries out a subroutine initial process is investigated as the conditions since the number of registers serving as the boundaries are different according to reservation or non-reservation of a local area at selection of the instruction. At non-reservation of the local area, the executing speed of a basic instruction is higher than that of a high function instruction with 3 registers to be saved and vice versa with 4 registers to be saved. At securing of the local area,the executing speed of the basic instruction is higher than the high function instruction with 5 registers to be saved and vice versa with 6 registers to be saved respectively. Therefore, the register value is set according to the conditions and the number of registers to be saved is checked. If the number of these registers is smaller than the conditional register value, an object code of the basic instruction is generated. Then an object code of the high function instruction is generated if the number of registers larger than the conditional register value. As a result, the executing speed is minimized in a data processing system.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、高級言語で書かれたプログラムを効率良く実
行できる自動翻訳装置におけるデータ処理方式に関する
ものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing method in an automatic translation device that can efficiently execute a program written in a high-level language.

〔従来の技術〕[Conventional technology]

高級言語において、使用傾度が高く処理が定形的なもの
は高機能命令として、マイクロプロセッサに備えられて
いる。従来の自動翻訳装置において、こういった高級言
語からオブジェクトコードを生成する際に、この高機能
命令を使って命令を生成していた。
In high-level languages, those that are frequently used and whose processing is fixed are provided in microprocessors as high-performance instructions. In conventional automatic translation devices, these high-performance instructions are used to generate instructions when generating object code from these high-level languages.

動作の一例として、手続きの初期処理を行ったときには
、レジスタの待避、フレームポインタの設定、ローカル
な領域の確保などを1命令で行う高機能命令を生成して
いた。
As an example of operation, when initial processing of a procedure is performed, a high-performance instruction is generated that performs tasks such as saving registers, setting a frame pointer, and securing a local area in one instruction.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来のデータ処理方式は以上のように高機能命令を使っ
ている。しかし場合によっては、命令の冗長な部分が多
くあるため、高機能命令から冗長な部分を省いた動作を
基本命令で実現するよりも実行速度が遅くなるという欠
点があづた。
Conventional data processing methods use high-performance instructions as described above. However, in some cases, there are many redundant parts of the instructions, resulting in a disadvantage that the execution speed is slower than if the basic instructions were used to perform an operation by omitting the redundant parts from the high-function instructions.

本発明は上記のような欠点を解消するためになされたも
ので、高機能命令を出力するときの条件によって、高機
能命令を出力するか、又は基本命令を出力するかを選択
し、より実行速度の速いオブジェクトコードを得ること
を目的とする。
The present invention has been made in order to solve the above-mentioned drawbacks, and it is possible to select whether to output high-function instructions or basic instructions depending on the conditions when outputting high-function instructions, so that the instructions can be executed more easily. The purpose is to obtain fast object code.

〔課題を解決するための手段〕[Means to solve the problem]

本発明に係るデータ処理方式は、高機能命令を出力する
際に、条件を判断する手段、高機能命令を出力する手段
、基本命令を出力する手段を備えたものである。
The data processing method according to the present invention includes means for determining conditions, means for outputting a high-performance command, and means for outputting a basic command when outputting a high-performance command.

〔作用〕[Effect]

本発明におけるデータ処理方式は条件調査1条件分岐を
設けたので、命令を選択することができ実行速度を常に
最短にすることができる。
Since the data processing method according to the present invention is provided with a conditional check 1 conditional branch, an instruction can be selected and the execution speed can always be kept at the shortest possible time.

〔実施例〕〔Example〕

以下、本発明の一実施例を図に従って説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第1図は本発明の一実施例を示したフローチャート図で
ある。命令を出力するとき条件調査で、分岐のための条
件を調査し境界条件を設定する。次にこの条件により分
岐し、高機能命令を実施するか基本命令群を実行するか
を選択し、オブジェクトコードを生成する。
FIG. 1 is a flowchart showing one embodiment of the present invention. When outputting an instruction, check conditions for branching and set boundary conditions. Next, the program branches based on this condition, selects whether to execute a high-function instruction or a group of basic instructions, and generates object code.

次に、第2図は第1図の実施例の1つとしてサブルーチ
ン初期処理における条件調査と条件分岐を表すフローチ
ャートである。第3図は第2図のフローチャートの条件
調査を示す図で、点線はローカルな領域を確保しなかっ
たとき、実線はローカルな領域を確保したときのレジス
タ数に対する実行速度を表している。
Next, FIG. 2 is a flowchart showing condition investigation and conditional branching in subroutine initial processing as one of the embodiments shown in FIG. FIG. 3 is a diagram showing a condition investigation of the flowchart of FIG. 2, where the dotted line represents the execution speed with respect to the number of registers when the local area is not secured, and the solid line represents the execution speed when the local area is secured.

第2図において、サブルーチン初期処理を行う命令を選
択するとき、第3図の様にローカルな領域を確保するか
しないかで境界となるレジスタ数が異なるため、条件と
して調査をする。ローカルな領域を確保しないときはレ
ジスタ数3のときまで基本命令群の方が速(、レジスタ
数4になると高機能命令の方が速い。またローカルな領
域を確保するときは、レジスタ数5のときまで基本命令
が速く、レジスタ数6になると高機能命令の方が実行速
度が速い。そこで条件によりレジスタ値を設定する。次
にマスクするレジスタ数を調べ、もし条件のレジスタ値
よりもマスクするレジスタ数が少なければ、基本命令群
を多ければ高機能命令のオブジェクトコードを生成する
In FIG. 2, when selecting an instruction to perform subroutine initial processing, the number of boundary registers differs depending on whether or not a local area is secured as shown in FIG. 3, so this is investigated as a condition. When the local area is not secured, the basic instructions are faster until the number of registers is 3 (and when the number of registers is 4, the high-function instructions are faster). Basic instructions are faster until the number of registers reaches 6, and high-function instructions are faster at execution speed when the number of registers reaches 6. Therefore, register values are set according to the condition.Next, check the number of registers to be masked, and if the number of registers to be masked is higher than the register value of the condition, the execution speed is faster. If the number of registers is small, if the number of basic instructions is large, object code of high-performance instructions is generated.

このように本方式は条件調査1条件分岐を設けることに
より、命令を選択することができ実行速度を最短にする
ことが可能となる。
In this manner, by providing the condition check 1 conditional branch, this system can select an instruction and minimize the execution speed.

〔発明の効果〕〔Effect of the invention〕

以上のように本発明によれば、高機能命令とそれに対応
する基本命令に分割するかを判断することにより、実行
速度を最短にすることが可能となる。
As described above, according to the present invention, it is possible to minimize the execution speed by determining whether to divide an instruction into a high-function instruction and a corresponding basic instruction.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示すデータ処理方式のフロ
ーチャート、第2図は第1図の実施例の1つとしてサブ
ルーチン初期処理における条件調査と条件分岐を示すフ
ローチャート、第3図は第2図に係る条件調査を示す図
である。
FIG. 1 is a flowchart of a data processing method showing one embodiment of the present invention, FIG. 2 is a flowchart showing condition investigation and conditional branching in subroutine initial processing as one of the embodiments of FIG. 1, and FIG. FIG. 2 is a diagram showing a condition investigation related to FIG. 2;

Claims (1)

【特許請求の範囲】[Claims] 高機能な命令を持つマイクロプロセッサにおいて、高級
言語からそのマイクロプロセッサのオブジェクトコード
を生成する自動翻訳装置において、高機能な命令、又は
それに対応する様に構成した基本命令群を生成し、その
実行速度が最速になる様に、オブジェクトコードを生成
することを特徴とするデータ処理方式。
For microprocessors with high-performance instructions, an automatic translation device that generates object code for the microprocessor from a high-level language generates high-performance instructions or a group of basic instructions configured to correspond to them, and speeds up their execution. A data processing method characterized by generating object code so that it is the fastest.
JP21622489A 1989-08-22 1989-08-22 Data processing system Pending JPH0378834A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21622489A JPH0378834A (en) 1989-08-22 1989-08-22 Data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21622489A JPH0378834A (en) 1989-08-22 1989-08-22 Data processing system

Publications (1)

Publication Number Publication Date
JPH0378834A true JPH0378834A (en) 1991-04-04

Family

ID=16685224

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21622489A Pending JPH0378834A (en) 1989-08-22 1989-08-22 Data processing system

Country Status (1)

Country Link
JP (1) JPH0378834A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7523897B2 (en) 2003-03-06 2009-04-28 I.C.M. Group Device for fixing a wire on a load bearing element provided with at least one opening

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7523897B2 (en) 2003-03-06 2009-04-28 I.C.M. Group Device for fixing a wire on a load bearing element provided with at least one opening

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