JPH0377462U - - Google Patents
Info
- Publication number
- JPH0377462U JPH0377462U JP1989139117U JP13911789U JPH0377462U JP H0377462 U JPH0377462 U JP H0377462U JP 1989139117 U JP1989139117 U JP 1989139117U JP 13911789 U JP13911789 U JP 13911789U JP H0377462 U JPH0377462 U JP H0377462U
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- semiconductor device
- circuit board
- gate electrode
- base plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims description 11
- 239000004020 conductor Substances 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Description
第１図は本考案の一実施例を示す半導体装置の
回路基板の断面図、第２図は半導体装置が機器に
組み込まれる際の接続状態を示す図、第３図は半
導体装置の回路構成図、第４図は半導体装置の断
面図、第５図は回路基板に半導体素子等を搭載し
た状態を示す平面図、第６図は従来の半導体装置
の回路基板の断面図である。
１……回路基板、３……ゲート電極、４……半
導体素子、６……制御素子、７……金属ベース板
、８……絶縁層、９……導電体、１１，１２……
ランド部、１９……凹部。
Fig. 1 is a cross-sectional view of a circuit board of a semiconductor device showing an embodiment of the present invention, Fig. 2 is a diagram showing a connection state when the semiconductor device is incorporated into equipment, and Fig. 3 is a circuit configuration diagram of the semiconductor device. 4 is a sectional view of a semiconductor device, FIG. 5 is a plan view showing a state in which semiconductor elements and the like are mounted on a circuit board, and FIG. 6 is a sectional view of a circuit board of a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1... Circuit board, 3... Gate electrode, 4... Semiconductor element, 6... Control element, 7... Metal base plate, 8... Insulating layer, 9... Conductor, 11, 12...
Land portion, 19... recessed portion.
Claims (1)
、制御素子等が搭載された半導体装置であつて、
前記回路基板は、金属ベース板と、該金属ベース
板上に積層された絶縁層と、該絶縁層上に固着形
成され前記半導体素子等が搭載される導電体とか
ら構成され、前記半導体素子のゲート電極が接続
された導電体直下の絶縁層の厚さ寸法が、その他
の部分の厚さ寸法に比べて大とされたことを特徴
とする半導体装置。 A semiconductor device in which a semiconductor element having a gate electrode, a control element, etc. are mounted on a circuit board,
The circuit board is composed of a metal base plate, an insulating layer laminated on the metal base plate, and a conductor fixedly formed on the insulating layer and on which the semiconductor element and the like are mounted. A semiconductor device characterized in that the thickness of an insulating layer directly under a conductor to which a gate electrode is connected is larger than the thickness of other parts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989139117U JPH0648878Y2 (en) | 1989-11-29 | 1989-11-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989139117U JPH0648878Y2 (en) | 1989-11-29 | 1989-11-29 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0377462U true JPH0377462U (en) | 1991-08-05 |
| JPH0648878Y2 JPH0648878Y2 (en) | 1994-12-12 |
Family
ID=31686178
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989139117U Expired - Fee Related JPH0648878Y2 (en) | 1989-11-29 | 1989-11-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0648878Y2 (en) |
-
1989
- 1989-11-29 JP JP1989139117U patent/JPH0648878Y2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0648878Y2 (en) | 1994-12-12 |
Similar Documents
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |