JPH0376791B2 - - Google Patents

Info

Publication number
JPH0376791B2
JPH0376791B2 JP60112259A JP11225985A JPH0376791B2 JP H0376791 B2 JPH0376791 B2 JP H0376791B2 JP 60112259 A JP60112259 A JP 60112259A JP 11225985 A JP11225985 A JP 11225985A JP H0376791 B2 JPH0376791 B2 JP H0376791B2
Authority
JP
Japan
Prior art keywords
superconducting
insulator
contact hole
etching
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60112259A
Other languages
English (en)
Japanese (ja)
Other versions
JPS61271880A (ja
Inventor
Shuichi Tawara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP60112259A priority Critical patent/JPS61271880A/ja
Publication of JPS61271880A publication Critical patent/JPS61271880A/ja
Publication of JPH0376791B2 publication Critical patent/JPH0376791B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00Superconducting devices
    • H10N60/01Manufacture or treatment

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
JP60112259A 1985-05-27 1985-05-27 超電導線路の形成方法 Granted JPS61271880A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60112259A JPS61271880A (ja) 1985-05-27 1985-05-27 超電導線路の形成方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60112259A JPS61271880A (ja) 1985-05-27 1985-05-27 超電導線路の形成方法

Publications (2)

Publication Number Publication Date
JPS61271880A JPS61271880A (ja) 1986-12-02
JPH0376791B2 true JPH0376791B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1991-12-06

Family

ID=14582227

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60112259A Granted JPS61271880A (ja) 1985-05-27 1985-05-27 超電導線路の形成方法

Country Status (1)

Country Link
JP (1) JPS61271880A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5817689A (ja) * 1981-07-24 1983-02-01 Fujitsu Ltd ジヨセフソン回路の製造方法
JPS605235A (ja) * 1983-06-23 1985-01-11 井関農機株式会社 穀粒供給装置

Also Published As

Publication number Publication date
JPS61271880A (ja) 1986-12-02

Similar Documents

Publication Publication Date Title
US4172004A (en) Method for forming dense dry etched multi-level metallurgy with non-overlapped vias
EP0100735A2 (en) Lift-off process for fabricating self-aligned contacts
US4040891A (en) Etching process utilizing the same positive photoresist layer for two etching steps
US4289834A (en) Dense dry etched multi-level metallurgy with non-overlapped vias
US4007103A (en) Planarizing insulative layers by resputtering
KR900001834B1 (ko) 반도체장치의 제조방법
EP0355339A2 (en) Process for making self-aligned contacts
CA1120611A (en) Forming interconnections for multilevel interconnection metallurgy systems
KR100435137B1 (ko) 두꺼운도체를갖는모노리식마이크로파집적회로를제조하는방법
US4698125A (en) Method of producing a layered structure
US5252177A (en) Method for forming a multilayer wiring of a semiconductor device
JPS6146081A (ja) ジヨセフソン接合素子の製造方法
KR19980033871A (ko) 반도체 장치의 제조 방법
JP2938341B2 (ja) 同軸構造の配線の形成方法
JPH0376791B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
KR950006343B1 (ko) 반도체 장치의 제조방법
JPH0374514B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
KR100278995B1 (ko) 반도체장치의 비어홀 형성방법
JPH0569308B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JPS6260241A (ja) 多層配線構造の製造方法
EP0168535B1 (en) A method of producing a layered structure
KR100365746B1 (ko) 콘택저항개선을위한반도체소자제조방법
US4693783A (en) Method of producing interconnections in a semiconductor integrated circuit structure
KR0182176B1 (ko) 반도체 소자의 접촉부 제조 공정
KR0167097B1 (ko) 반도체 장치의 금속 배선막 형성 방법

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term