JPH0375542U - - Google Patents

Info

Publication number
JPH0375542U
JPH0375542U JP13755589U JP13755589U JPH0375542U JP H0375542 U JPH0375542 U JP H0375542U JP 13755589 U JP13755589 U JP 13755589U JP 13755589 U JP13755589 U JP 13755589U JP H0375542 U JPH0375542 U JP H0375542U
Authority
JP
Japan
Prior art keywords
glass plate
sealed
optical device
package
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13755589U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP13755589U priority Critical patent/JPH0375542U/ja
Publication of JPH0375542U publication Critical patent/JPH0375542U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例の断面図、第2図は
本考案の参考例の断面図、第3図は従来のセラミ
ツクパツケージの断面図である。 1……半導体光素子チツプ、2……リードフレ
ーム、2A……セラミツクパツケージ、3……ボ
ンデイング配線、4……透明エポキシ樹脂、4A
……エポキシ樹脂、4B……キヤツプガラス、5
……ガラス板。
FIG. 1 is a sectional view of an embodiment of the present invention, FIG. 2 is a sectional view of a reference example of the present invention, and FIG. 3 is a sectional view of a conventional ceramic package. 1... Semiconductor optical device chip, 2... Lead frame, 2A... Ceramic package, 3... Bonding wiring, 4... Transparent epoxy resin, 4A
...Epoxy resin, 4B...Cap glass, 5
...Glass plate.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 光素子表面にガラス板を直接搭載して封止し、
前記ガラス板が搭載されていない前記光素子表面
の残りの領域を樹脂で封したことを特徴とする光
素子用パツケージ。
A glass plate is mounted directly on the surface of the optical element and sealed.
A package for an optical device, characterized in that the remaining area of the surface of the optical device on which the glass plate is not mounted is sealed with a resin.
JP13755589U 1989-11-27 1989-11-27 Pending JPH0375542U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13755589U JPH0375542U (en) 1989-11-27 1989-11-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13755589U JPH0375542U (en) 1989-11-27 1989-11-27

Publications (1)

Publication Number Publication Date
JPH0375542U true JPH0375542U (en) 1991-07-29

Family

ID=31684707

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13755589U Pending JPH0375542U (en) 1989-11-27 1989-11-27

Country Status (1)

Country Link
JP (1) JPH0375542U (en)

Similar Documents

Publication Publication Date Title
JPH0375542U (en)
JPS61144650U (en)
JPH01140850U (en)
JPH029461U (en)
JPS6364046U (en)
JPS61182036U (en)
JPH0263544U (en)
JPH0375539U (en)
JPS60153538U (en) semiconductor element
JPH0267658U (en)
JPH0313748U (en)
JPH0385673U (en)
JPH0256450U (en)
JPH01121956U (en)
JPS6439643U (en)
JPS6430854U (en)
JPH0385648U (en)
JPH0195767U (en)
JPS6268246U (en)
JPH01121953U (en)
JPH0270446U (en)
JPH0252443U (en)
JPH01104720U (en)
JPH0279046U (en)
JPH0247053U (en)