JPH01121956U - - Google Patents
Info
- Publication number
- JPH01121956U JPH01121956U JP1721788U JP1721788U JPH01121956U JP H01121956 U JPH01121956 U JP H01121956U JP 1721788 U JP1721788 U JP 1721788U JP 1721788 U JP1721788 U JP 1721788U JP H01121956 U JPH01121956 U JP H01121956U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- semiconductor device
- substrate
- moisture
- extended
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 claims 1
- 229920003002 synthetic resin Polymers 0.000 claims 1
- 239000000057 synthetic resin Substances 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Solid State Image Pick-Up Elements (AREA)
Description
第1図は本考案に係る半導体装置の実施例を示
す断面図、第2図は従来例を示す断面図、第3図
は第2図の従来例の改良試考例を示す断面図であ
る。
1……基板、2……ICチツプ、3……リード
系、5……フイルム、W……透光部。
FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention, FIG. 2 is a sectional view showing a conventional example, and FIG. 3 is a sectional view showing an improved trial example of the conventional example shown in FIG. . 1...Substrate, 2...IC chip, 3...Lead system, 5...Film, W...Transparent part.
Claims (1)
る実装構造を備えた半導体装置において、合成樹
脂製の基板に載置されるICチツプの表面に透明
性、耐湿性の高い材質からなるフイルムを被着す
ると共に、ICチツプに接続されるリード系を基
板の側方へ引出したことを特徴とする半導体装置
。 In a semiconductor device equipped with a mounting structure having a transparent part that allows light to pass through the IC chip, a film made of a highly transparent and moisture-resistant material is placed on the surface of the IC chip mounted on a synthetic resin substrate. 1. A semiconductor device characterized in that a lead system connected to an IC chip is extended to the side of the substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1721788U JPH01121956U (en) | 1988-02-10 | 1988-02-10 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1721788U JPH01121956U (en) | 1988-02-10 | 1988-02-10 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01121956U true JPH01121956U (en) | 1989-08-18 |
Family
ID=31230802
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1721788U Pending JPH01121956U (en) | 1988-02-10 | 1988-02-10 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01121956U (en) |
-
1988
- 1988-02-10 JP JP1721788U patent/JPH01121956U/ja active Pending
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