JPH0370416B2 - - Google Patents

Info

Publication number
JPH0370416B2
JPH0370416B2 JP63290385A JP29038588A JPH0370416B2 JP H0370416 B2 JPH0370416 B2 JP H0370416B2 JP 63290385 A JP63290385 A JP 63290385A JP 29038588 A JP29038588 A JP 29038588A JP H0370416 B2 JPH0370416 B2 JP H0370416B2
Authority
JP
Japan
Prior art keywords
parity
bit
adder
output
value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP63290385A
Other languages
English (en)
Japanese (ja)
Other versions
JPH01220528A (ja
Inventor
Buraian Burotsudonatsukusu Teimoshii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPH01220528A publication Critical patent/JPH01220528A/ja
Publication of JPH0370416B2 publication Critical patent/JPH0370416B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50Adding; Subtracting
    • G06F7/505Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Correction Of Errors (AREA)
JP63290385A 1988-02-17 1988-11-18 パリテイ発生器 Granted JPH01220528A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US156626 1988-02-17
US07/156,626 US4879675A (en) 1988-02-17 1988-02-17 Parity generator circuit and method

Publications (2)

Publication Number Publication Date
JPH01220528A JPH01220528A (ja) 1989-09-04
JPH0370416B2 true JPH0370416B2 (en, 2012) 1991-11-07

Family

ID=22560357

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63290385A Granted JPH01220528A (ja) 1988-02-17 1988-11-18 パリテイ発生器

Country Status (3)

Country Link
US (1) US4879675A (en, 2012)
EP (1) EP0328899A3 (en, 2012)
JP (1) JPH01220528A (en, 2012)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5557622A (en) * 1990-10-01 1996-09-17 Digital Equipment Corporation Method and apparatus for parity generation
US5608741A (en) * 1993-11-23 1997-03-04 Intel Corporation Fast parity generator using complement pass-transistor logic
FR2713364B1 (fr) * 1993-11-30 1996-01-12 Bull Sa Dispositif de calcul des bits de parité associés à une somme de deux nombres.
US5825204A (en) * 1996-03-21 1998-10-20 Hashimoto; Masashi Apparatus and method for a party check logic circuit in a dynamic random access memory
KR100224278B1 (ko) * 1996-12-18 1999-10-15 윤종용 패스 트랜지스터 로직을 사용하는 조건 합 가산기 및 그것을 구비한 집적 회로
US6990507B2 (en) * 2002-05-21 2006-01-24 Hewlett-Packard Development Company, L.P. Parity prediction for arithmetic increment function

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3222652A (en) * 1961-08-07 1965-12-07 Ibm Special-function data processing
US3342983A (en) * 1963-06-25 1967-09-19 Ibm Parity checking and parity generating means for binary adders
GB1047246A (en, 2012) * 1963-02-27
US3287546A (en) * 1963-02-27 1966-11-22 Ibm Parity prediction apparatus for use with a binary adder
US3596072A (en) * 1968-05-24 1971-07-27 Hitachi Ltd Error-detecting circuitry in adder system
US3758760A (en) * 1972-04-07 1973-09-11 Honeywell Inf Systems Error detection for arithmetic and logical unit modules
US3925647A (en) * 1974-09-30 1975-12-09 Honeywell Inf Systems Parity predicting and checking logic for carry look-ahead binary adder
US4224680A (en) * 1978-06-05 1980-09-23 Fujitsu Limited Parity prediction circuit for adder/counter
US4608693A (en) * 1984-05-07 1986-08-26 At&T Bell Laboratories Fault detection arrangement for a digital conferencing system

Also Published As

Publication number Publication date
EP0328899A2 (en) 1989-08-23
JPH01220528A (ja) 1989-09-04
EP0328899A3 (en) 1991-09-11
US4879675A (en) 1989-11-07

Similar Documents

Publication Publication Date Title
JP3244506B2 (ja) 小型乗算器
US3993891A (en) High speed parallel digital adder employing conditional and look-ahead approaches
JPS6053329B2 (ja) 加算装置
US4556948A (en) Multiplier speed improvement by skipping carry save adders
EP0642093B1 (en) Method, system and apparatus for automatically designing a multiplier circuit and multiplier circuit designed by performing said method
EP0416869B1 (en) Digital adder/accumulator
JPH0421889B2 (en, 2012)
US4293922A (en) Device for multiplying binary numbers
US5497343A (en) Reducing the number of carry-look-ahead adder stages in high-speed arithmetic units, structure and method
EP0605885B1 (en) Method and apparatus for automatically designing logic circuit, and multiplier
JPH0370416B2 (en, 2012)
US3842250A (en) Circuit for implementing rounding in add/subtract logic networks
JPH06236255A (ja) 並列桁上げ発生ネットワーク、並列加算器ネットワーク、桁上げ発生モジュール、マルチビット加算器ネットワークおよびモジュラー桁上げ伝ぱんユニット
JPH09222991A (ja) 加算方法および加算器
US4549280A (en) Apparatus for creating a multiplication pipeline of arbitrary size
JPH0366693B2 (en, 2012)
JPH056263A (ja) 加算器およびその加算器を用いた絶対値演算回路
JPH0454256B2 (en, 2012)
JP3210420B2 (ja) 整数上の乗算回路
JP3315042B2 (ja) 乗算装置
JP3207490B2 (ja) 加算回路及びそれを使用したnビット加算器
JPH05108308A (ja) 乗算回路
JPH04232529A (ja) 多重ディジット10進数を2進数に変換する装置および統一された比復号器
JP3106525B2 (ja) 加算方式及びその回路
SU1179322A1 (ru) Устройство дл умножени двух чисел

Legal Events

Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 19920428