JPH0366693B2 - - Google Patents

Info

Publication number
JPH0366693B2
JPH0366693B2 JP58154000A JP15400083A JPH0366693B2 JP H0366693 B2 JPH0366693 B2 JP H0366693B2 JP 58154000 A JP58154000 A JP 58154000A JP 15400083 A JP15400083 A JP 15400083A JP H0366693 B2 JPH0366693 B2 JP H0366693B2
Authority
JP
Japan
Prior art keywords
carry
pair
block
adder
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58154000A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5957343A (ja
Inventor
Ei Uea Furederitsuku
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JPS5957343A publication Critical patent/JPS5957343A/ja
Publication of JPH0366693B2 publication Critical patent/JPH0366693B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/74—Selecting or encoding within a word the position of one or more bits having a specified value, e.g. most or least significant one or zero detection, priority encoders
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/5055—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination in which one operand is a constant, i.e. incrementers or decrementers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/506—Indexing scheme relating to groups G06F7/506 - G06F7/508
    • G06F2207/5063—2-input gates, i.e. only using 2-input logical gates, e.g. binary carry look-ahead, e.g. Kogge-Stone or Ladner-Fischer adder

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • Complex Calculations (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
JP15400083A 1982-08-23 1983-08-23 加算回路 Granted JPS5957343A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US41080782A 1982-08-23 1982-08-23
US410807 1995-03-27

Related Child Applications (5)

Application Number Title Priority Date Filing Date
JP2341184A Division JPH03228120A (ja) 1982-08-23 1990-11-30 増分器
JP2341186A Division JPH03228122A (ja) 1982-08-23 1990-11-30 加算回路
JP2341187A Division JPH03229320A (ja) 1982-08-23 1990-11-30 増分回路
JP2341188A Division JPH03229321A (ja) 1982-08-23 1990-11-30 プライオリティ・エンコーダ
JP2341185A Division JPH03228121A (ja) 1982-08-23 1990-11-30 プライオリティ・エンコーダ

Publications (2)

Publication Number Publication Date
JPS5957343A JPS5957343A (ja) 1984-04-02
JPH0366693B2 true JPH0366693B2 (en, 2012) 1991-10-18

Family

ID=23626312

Family Applications (6)

Application Number Title Priority Date Filing Date
JP15400083A Granted JPS5957343A (ja) 1982-08-23 1983-08-23 加算回路
JP2341184A Granted JPH03228120A (ja) 1982-08-23 1990-11-30 増分器
JP2341185A Granted JPH03228121A (ja) 1982-08-23 1990-11-30 プライオリティ・エンコーダ
JP2341188A Granted JPH03229321A (ja) 1982-08-23 1990-11-30 プライオリティ・エンコーダ
JP2341186A Granted JPH03228122A (ja) 1982-08-23 1990-11-30 加算回路
JP2341187A Granted JPH03229320A (ja) 1982-08-23 1990-11-30 増分回路

Family Applications After (5)

Application Number Title Priority Date Filing Date
JP2341184A Granted JPH03228120A (ja) 1982-08-23 1990-11-30 増分器
JP2341185A Granted JPH03228121A (ja) 1982-08-23 1990-11-30 プライオリティ・エンコーダ
JP2341188A Granted JPH03229321A (ja) 1982-08-23 1990-11-30 プライオリティ・エンコーダ
JP2341186A Granted JPH03228122A (ja) 1982-08-23 1990-11-30 加算回路
JP2341187A Granted JPH03229320A (ja) 1982-08-23 1990-11-30 増分回路

Country Status (3)

Country Link
JP (6) JPS5957343A (en, 2012)
DE (1) DE3326388A1 (en, 2012)
GB (3) GB2130771B (en, 2012)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6055438A (ja) * 1983-09-05 1985-03-30 Matsushita Electric Ind Co Ltd ２入力加算器
JPS6275840A (ja) * 1985-09-30 1987-04-07 Toshiba Corp 桁上げ選択加算器
EP0352549B1 (de) * 1988-07-29 1995-06-07 Siemens Aktiengesellschaft Carry-select-Addierer
US4956802A (en) * 1988-12-14 1990-09-11 Sun Microsystems, Inc. Method and apparatus for a parallel carry generation adder
US5136539A (en) * 1988-12-16 1992-08-04 Intel Corporation Adder with intermediate carry circuit
JPH0651950A (ja) * 1992-07-30 1994-02-25 Mitsubishi Electric Corp 加算回路
US6527748B1 (en) 1998-08-17 2003-03-04 Yutaka Suzuki Method of gastrostomy, and an infection preventive cover, kit or catheter kit, and a gastrostomy catheter kit

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3078337A (en) * 1958-12-17 1963-02-19 Skiatron Elect & Tele Metering systems
US3138703A (en) * 1959-12-29 1964-06-23 Ibm Full adder
DE1231311B (de) * 1964-11-17 1966-12-29 Siemens Ag Schaltungsanordnung zum Umwerten von Informationen, insbesondere fuer Zeitmultiplex-Fernsprechvermittlungssysteme
US3316393A (en) * 1965-03-25 1967-04-25 Honeywell Inc Conditional sum and/or carry adder
GB1143886A (en, 2012) * 1966-10-13
GB1391175A (en) * 1971-08-04 1975-04-16 Cambridge Consultants Lttd Electrical circuit means for use in acoustic emission detecting and or recording apparatus
GB1479939A (en) * 1973-09-25 1977-07-13 Siemens Ag Programme-controlled data switching systems
JPS537349B2 (en, 2012) * 1974-03-27 1978-03-16
JPS5446224U (en, 2012) * 1977-09-07 1979-03-30
EP0052157A1 (de) * 1980-11-15 1982-05-26 Deutsche ITT Industries GmbH Binärer MOS-Carry-Look-Ahead-Paralleladdierer

Also Published As

Publication number Publication date
JPH03228120A (ja) 1991-10-09
JPH0467213B2 (en, 2012) 1992-10-27
JPH03228122A (ja) 1991-10-09
JPH0467212B2 (en, 2012) 1992-10-27
JPH03229320A (ja) 1991-10-11
GB2127187A (en) 1984-04-04
GB2130771A (en) 1984-06-06
JPH03229321A (ja) 1991-10-11
JPH03228121A (ja) 1991-10-09
GB8330888D0 (en) 1983-12-29
GB2130771B (en) 1986-02-12
JPH0450615B2 (en, 2012) 1992-08-14
JPH0467211B2 (en, 2012) 1992-10-27
DE3326388A1 (de) 1984-02-23
GB8330889D0 (en) 1983-12-29
JPH0450614B2 (en, 2012) 1992-08-14
JPS5957343A (ja) 1984-04-02
GB8306208D0 (en) 1983-04-13
GB2130774B (en) 1986-02-12
GB2130774A (en) 1984-06-06
DE3326388C2 (en, 2012) 1993-04-01
GB2127187B (en) 1986-03-05

Similar Documents

Publication Publication Date Title
US4623982A (en) Conditional carry techniques for digital processors
JP3244506B2 (ja) 小型乗算器
JPH0479013B2 (en, 2012)
JPS6055438A (ja) ２入力加算器
US20020143841A1 (en) Multiplexer based parallel n-bit adder circuit for high speed processing
US6578063B1 (en) 5-to-2 binary adder
JPS595349A (ja) 加算器
US6584485B1 (en) 4 to 2 adder
JPH0366693B2 (en, 2012)
JPH02293929A (ja) デジタルシステム乗算の方法及び装置
JPH0552530B2 (en, 2012)
US3842250A (en) Circuit for implementing rounding in add/subtract logic networks
JP2554452B2 (ja) 自己検査型補数加算器ユニット
US5636156A (en) Adder with improved carry lookahead structure
US5257217A (en) Area-efficient multiplier for use in an integrated circuit
JP2001501341A (ja) デジタル加算器回路
Ykuntam et al. Design of 32-bit carry select adder with reduced area
US6484193B1 (en) Fully pipelined parallel multiplier with a fast clock cycle
JP3741280B2 (ja) 桁上げ先見回路およびこれを用いた加算回路
US7240085B2 (en) Faster shift value calculation using modified carry-lookahead adder
JPH056892B2 (en, 2012)
JPH01304542A (ja) パリテイ予測回路
US6631393B1 (en) Method and apparatus for speculative addition using a limited carry
JPS6261120A (ja) けた上げ選択加算器
JP2563473B2 (ja) ２進演算器