JPH0421889B2 - - Google Patents

Info

Publication number
JPH0421889B2
JPH0421889B2 JP59165263A JP16526384A JPH0421889B2 JP H0421889 B2 JPH0421889 B2 JP H0421889B2 JP 59165263 A JP59165263 A JP 59165263A JP 16526384 A JP16526384 A JP 16526384A JP H0421889 B2 JPH0421889 B2 JP H0421889B2
Authority
JP
Japan
Prior art keywords
carry
signal
circuit
input
bits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59165263A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6143341A (ja
Inventor
Masaaki Yano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP59165263A priority Critical patent/JPS6143341A/ja
Priority to US06/763,117 priority patent/US4764886A/en
Publication of JPS6143341A publication Critical patent/JPS6143341A/ja
Publication of JPH0421889B2 publication Critical patent/JPH0421889B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/3896—Bit slicing

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
JP59165263A 1984-08-07 1984-08-07 加算回路 Granted JPS6143341A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP59165263A JPS6143341A (ja) 1984-08-07 1984-08-07 加算回路
US06/763,117 US4764886A (en) 1984-08-07 1985-08-07 Bit slice - type arithmetic adder circuit using exclusive-or logic for use with a look-ahead circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59165263A JPS6143341A (ja) 1984-08-07 1984-08-07 加算回路

Publications (2)

Publication Number Publication Date
JPS6143341A JPS6143341A (ja) 1986-03-01
JPH0421889B2 true JPH0421889B2 (en, 2012) 1992-04-14

Family

ID=15809004

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59165263A Granted JPS6143341A (ja) 1984-08-07 1984-08-07 加算回路

Country Status (2)

Country Link
US (1) US4764886A (en, 2012)
JP (1) JPS6143341A (en, 2012)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5047974A (en) * 1987-11-24 1991-09-10 Harris Corporation Cell based adder with tree structured carry, inverting logic and balanced loading
US4858168A (en) * 1988-02-16 1989-08-15 American Telephone And Telegraph Company Carry look-ahead technique having a reduced number of logic levels
US5122982A (en) * 1988-02-29 1992-06-16 Chopp Computer Corporation Carry generation method and apparatus
WO1989008294A1 (en) * 1988-02-29 1989-09-08 Chopp Computer Corporation Carry generation method and apparatus
US4982352A (en) * 1988-06-17 1991-01-01 Bipolar Integrated Technology, Inc. Methods and apparatus for determining the absolute value of the difference between binary operands
US5166899A (en) * 1990-07-18 1992-11-24 Hewlett-Packard Company Lookahead adder
JP2990791B2 (ja) * 1990-11-20 1999-12-13 ソニー株式会社 コレクタドットアンド回路
FR2693287B1 (fr) * 1992-07-03 1994-09-09 Sgs Thomson Microelectronics Sa Procédé pour effectuer des calculs numériques, et unité arithmétique pour la mise en Óoeuvre de ce procédé.
US5278783A (en) * 1992-10-30 1994-01-11 Digital Equipment Corporation Fast area-efficient multi-bit binary adder with low fan-out signals
US5497343A (en) * 1993-08-05 1996-03-05 Hyundai Electronics America Reducing the number of carry-look-ahead adder stages in high-speed arithmetic units, structure and method
WO1997008614A1 (en) * 1995-08-28 1997-03-06 Motorola Inc. Method and system for performing an l1 norm operation
US5944777A (en) * 1997-05-05 1999-08-31 Intel Corporation Method and apparatus for generating carries in an adder circuit
US6175852B1 (en) * 1998-07-13 2001-01-16 International Business Machines Corporation High-speed binary adder
US7016932B2 (en) * 2000-10-26 2006-03-21 Idaho State University Adders and adder bit blocks having an internal propagation characteristic independent of a carry input to the bit block and methods for using the same
JP2004013270A (ja) * 2002-06-04 2004-01-15 Oki Electric Ind Co Ltd 桁上げ先見加算器
KR100513160B1 (ko) * 2003-10-28 2005-09-08 한국전자통신연구원 감소된 면적을 갖는 캐리 예측 가산기
US8521801B2 (en) * 2008-04-28 2013-08-27 Altera Corporation Configurable hybrid adder circuitry
US7557614B1 (en) 2008-07-15 2009-07-07 International Business Machines Corporation Topology for a n-way XOR/XNOR circuit

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IL59907A0 (en) * 1980-04-23 1980-06-30 Nathan Grundland Arithmetic logic unit
JPS5739448A (en) * 1980-08-19 1982-03-04 Rikagaku Kenkyusho Carrying circuit of binary adder
US4504924A (en) * 1982-06-28 1985-03-12 International Business Machines Corporation Carry lookahead logical mechanism using affirmatively referenced transfer gates
US4623981A (en) * 1983-09-20 1986-11-18 Digital Equipment Corporation ALU with carry length detection

Also Published As

Publication number Publication date
US4764886A (en) 1988-08-16
JPS6143341A (ja) 1986-03-01

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