JPH0370378B2 - - Google Patents
Info
- Publication number
- JPH0370378B2 JPH0370378B2 JP62078713A JP7871387A JPH0370378B2 JP H0370378 B2 JPH0370378 B2 JP H0370378B2 JP 62078713 A JP62078713 A JP 62078713A JP 7871387 A JP7871387 A JP 7871387A JP H0370378 B2 JPH0370378 B2 JP H0370378B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate bias
- potential
- generation circuit
- transistor
- input protection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 39
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000003990 capacitor Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000010355 oscillation Effects 0.000 description 3
- 238000005513 bias potential Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
本発明は、半導体装置の入力保護装置に関する
もので、特に基板バイアス発生回路の入力保護に
使用されるものである。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an input protection device for a semiconductor device, and is particularly used for input protection of a substrate bias generation circuit.
（従来の技術）
一般に基板バイアス発生回路は、Ｎチヤンネ
ル・トランジスタの場合、基準電位（GND）よ
り低い電位を基板バイアスとして与えるものであ
り、多くの製品に使用されている。第２図に基板
バイアス発生回路の一例を示す。即ち発振回路１
の出力を、チヤージ・ポンプ・キヤパシタ２の入
力端に接続する。前記チヤージ・ポンプ・キヤパ
シタ２の出力端３を、第１のトランジスタ４の２
端子および第２のトランジスタ５の１端子に接続
し、第１のトランジスタ４の他の１端子を基準電
位６に接続し、第２のトランジスタ５の別の２端
子を基板バイアス発生回路の出力端７に接続す
る。(Prior Art) Generally, in the case of an N-channel transistor, a substrate bias generation circuit applies a potential lower than a reference potential (GND) as a substrate bias, and is used in many products. FIG. 2 shows an example of a substrate bias generation circuit. That is, oscillation circuit 1
The output of the charge pump capacitor 2 is connected to the input terminal of the charge pump capacitor 2. The output terminal 3 of the charge pump capacitor 2 is connected to the output terminal 3 of the first transistor 4.
terminal and one terminal of the second transistor 5, the other one terminal of the first transistor 4 is connected to the reference potential 6, and the other two terminals of the second transistor 5 are connected to the output terminal of the substrate bias generation circuit. Connect to 7.
すなわち、前記発振回路１によつて発生した連
続パルスを、前記キヤパシタ２によつて前記出力
端３を遷移さるせる。前記出力端３の電位が前記
基準電位６よりも高くなつた場合、前記第１のト
ランジスタ４がオン状態になり、前記基準電位６
に電流を流し、前記出力端３の電位を前記基準電
位にする。逆に、前記出力端３の電位が前記基準
電位６よりも低い場合、前記第１のトランジスタ
４はオフ状態になり、前記出力端３の電位を保持
する。 That is, the continuous pulses generated by the oscillation circuit 1 are caused to transition at the output terminal 3 by the capacitor 2. When the potential of the output terminal 3 becomes higher than the reference potential 6, the first transistor 4 is turned on and the reference potential 6 becomes higher.
A current is applied to the output terminal 3 to bring the potential of the output terminal 3 to the reference potential. Conversely, when the potential of the output terminal 3 is lower than the reference potential 6, the first transistor 4 is turned off and the potential of the output terminal 3 is maintained.
次に、前記基板バイアス発生回路の出力端７の
電位が前記出力端３より高い場合、前記第２のト
ランジスタ５がオン状態になり、前記基板バイア
ス出力端７の電位を、前記出力端３の電位にす
る。逆に、前記基板バイアス出力端７の電位が前
記出力端３よりも低い場合、前記第２のトランジ
スタ５はオフ状態になり、前記基板バイアス出力
端７の電位を保持する。 Next, when the potential of the output terminal 7 of the substrate bias generation circuit is higher than the output terminal 3, the second transistor 5 is turned on, and the potential of the substrate bias output terminal 7 is changed to the potential of the output terminal 3. to potential. Conversely, when the potential of the substrate bias output terminal 7 is lower than that of the output terminal 3, the second transistor 5 is turned off and the potential of the substrate bias output terminal 7 is maintained.
以上のようにして、前記基板バイアス回路出力
端子７の電位はマイナス電位に保持される。 As described above, the potential of the substrate bias circuit output terminal 7 is held at a negative potential.
（発明が解決しようとする問題点）
従来、基板バイアス発生回路の外部への出力端
子には、静電破壊の入力保護装置が設けられてい
なかつたため、静電破壊に対して弱かつた。即ち
基板バイアス発生回路に入力保護装置が設けられ
ていなかつた理由は、以下の理由による。(Problems to be Solved by the Invention) Conventionally, an output terminal to the outside of a substrate bias generation circuit has not been provided with an input protection device for electrostatic damage, making it vulnerable to electrostatic damage. That is, the reason why the input protection device was not provided in the substrate bias generation circuit is as follows.
従来の集積回路の内部回路の入力保護装置は、
第３図に示されるようなトランジスタを接続した
ものであつた。即ち、入力保護トランジスタ１０
の一端に外部への端子７′を接続し、他の２端子
を基板電位６に接続する。外部端子に非常に高い
電位が加わつた場合、前記トランジスタ１０のブ
レークダウン特性によつて、前記基準電位６に電
流を流し、ICの内部回路１１を保護する。前記
外部端子７′に基準電位６より低い電位が加われ
ば、前記トランジスタ１０がオン状態になり、前
記外部端子７′の電位を前記基準電位６にする。 Conventional integrated circuit internal circuit input protection devices are
It was constructed by connecting transistors as shown in FIG. That is, the input protection transistor 10
A terminal 7' to the outside is connected to one end, and the other two terminals are connected to the substrate potential 6. When a very high potential is applied to the external terminal, the breakdown characteristics of the transistor 10 cause a current to flow to the reference potential 6, thereby protecting the internal circuit 11 of the IC. When a potential lower than the reference potential 6 is applied to the external terminal 7', the transistor 10 is turned on and the potential of the external terminal 7' is set to the reference potential 6.
従来の入力保護装置を、基板バイアス発生回路
に接続した場合、基板バイアス発生回路が発生さ
せたマイナス電位を、入力保護装置によつて、基
準電位にしてしまい、使用できないものであつ
た。 When a conventional input protection device is connected to a substrate bias generation circuit, the negative potential generated by the substrate bias generation circuit is made into a reference potential by the input protection device, making it unusable.
そこで本発明は、基板バイアス発生回路の特性
をそこなうことなく、入力保護を行なうことを目
的とする。 Therefore, it is an object of the present invention to provide input protection without impairing the characteristics of the substrate bias generation circuit.
（問題点を解決するための手段と作用）
本発明は、バイアス発生回路をチツプ上に持つ
半導体装置において、前記基板バイアス発生回路
の出力端子と電源端子の間に入力保護用MOSト
ランジスタを接続し前記トランジスタの入力ゲー
トを前記基板バイアス回路の出力端子に接続した
ことを特徴とする半導体入力保護装置である。即
ち本発明は、基板バイアス発生回路によつて発生
すべき電位においては、前記入力保護用MOSト
ランジスタはオフして何ら影響を与えず、基板バ
イアス発生回路の外部端子に基板バイアス範囲外
の電位が加わつた場合に、前記トランジスタによ
り基板バイアス発生回路を保護するようにしたも
のである。
(Means and effects for solving the problems) The present invention provides a semiconductor device having a bias generation circuit on a chip, in which an input protection MOS transistor is connected between the output terminal and the power supply terminal of the substrate bias generation circuit. The semiconductor input protection device is characterized in that an input gate of the transistor is connected to an output terminal of the substrate bias circuit. That is, in the present invention, when the potential is to be generated by the substrate bias generation circuit, the input protection MOS transistor is turned off and has no effect, and a potential outside the substrate bias range is applied to the external terminal of the substrate bias generation circuit. In this case, the transistor protects the substrate bias generation circuit when the substrate bias is applied.
（実施例）
以下図面を参照して本発明の一実施例を説明す
る。第１図は同実施例の回路図であるが、これは
第２図のものと対応する場合の例であるから、対
応個所には同一符号を付して説明を省略し、特徴
とする点の説明を行なう。即ち基板バイアス発生
回路の出力端７に入力保護トランジスタ２０のゲ
ートとソースを接続と、ドレインを基準電位６に
接続する。別の入力保護トランジスタ２１のゲー
トとソースも、前記基板バイアス発生回路出力端
７に接続し、ドレインは電源８に接続する。(Example) An example of the present invention will be described below with reference to the drawings. Fig. 1 is a circuit diagram of the same embodiment, but since this is an example of a case corresponding to that in Fig. 2, corresponding parts are given the same reference numerals and explanations are omitted. I will explain. That is, the gate and source of the input protection transistor 20 are connected to the output terminal 7 of the substrate bias generation circuit, and the drain is connected to the reference potential 6. The gate and source of another input protection transistor 21 are also connected to the substrate bias generation circuit output terminal 7, and the drain is connected to the power supply 8.
しかして第１図の回路において、基板バイアス
発生回路の外部端子７に、基板バイアス電位より
も非常に低い電位が加わつた場合、主に前記入力
保護トランジスタ２１あるいは前記別の入力保護
トランジスタ２０のブレークダウン特性によつて
電流を流し、基板バイアス発生回路を保護する。 Therefore, in the circuit shown in FIG. 1, when a potential much lower than the substrate bias potential is applied to the external terminal 7 of the substrate bias generation circuit, a break occurs mainly in the input protection transistor 21 or the other input protection transistor 20. The down characteristic allows current to flow and protects the substrate bias generation circuit.
前記基板バイアス発生回路の外部端子７に、基
準電位６より高い電位が加わつた場合、主に前記
入力保護トランジスタ２０あるいは前記別の入力
保護トランジスタ２１がオン状態になつて電流を
流し、基準電位６あるいは電源８の電位にして、
基板バイアス発生回路を保護する。 When a potential higher than the reference potential 6 is applied to the external terminal 7 of the substrate bias generation circuit, the input protection transistor 20 or the other input protection transistor 21 mainly turns on, causing current to flow, and increasing the reference potential 6. Or, set it to the potential of power supply 8,
Protects the substrate bias generation circuit.
そして、基板バイアス発生回路によつて発生す
べき電位においては、前記入力保護トランジスタ
２０および前記別の入力保護トランジスタ２１は
オフしており、外部端子７には影響を与えない。
さらに入力保護装置は、外部端子７における基準
電位より高い電圧をカツトするため、基板バイア
ス発生回路の動作開始時の特性が良くなる利点を
持つものである。 At the potential to be generated by the substrate bias generation circuit, the input protection transistor 20 and the other input protection transistor 21 are off, and the external terminal 7 is not affected.
Furthermore, since the input protection device cuts off a voltage higher than the reference potential at the external terminal 7, it has the advantage that the characteristics of the substrate bias generation circuit at the start of operation are improved.
なお本発明は実施例のみに限られることなく
種々の応用が可能である。例えば実施例では、入
力保護トランジスタ２１，２２をＮチヤンネルと
したがＰチヤンネルを用いた基板バイアス発生回
路の場合、トランジスタ２１，２２をＰチヤンネ
ルMOSトランジスタで置きかえることもできる。
また本発明にあつてはトランジスタ２１，２２の
うちいずれか一方を用いる場合にも適用できる。 Note that the present invention is not limited to the embodiments, and can be applied in various ways. For example, in the embodiment, the input protection transistors 21 and 22 are N-channel, but in the case of a substrate bias generation circuit using a P-channel, the transistors 21 and 22 may be replaced with P-channel MOS transistors.
Furthermore, the present invention can also be applied to the case where either one of the transistors 21 and 22 is used.
以上説明した如く本発明によれば、基板バイア
ス発生回路の特性を損なうことなく、入力保護を
行なうことができるものである。
As described above, according to the present invention, input protection can be performed without impairing the characteristics of the substrate bias generation circuit.
第１図は本発明の一実施例の回路図、第２図は
従来の基板バイアス発生回路図、第３図は従来の
入力保護装置を示す回路図である。
１…発振回路、２…チヤージ・ポンプ・キヤパ
シタ、３…チヤージ・ポンプ・キヤパシタの出力
端、４，５…Ｎチヤンネルトランジスタ、６…基
準電圧、７…基板バイアス発生回路出力端、８…
電源、２０，２１…入力保護トランジスタ。
FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a conventional substrate bias generation circuit diagram, and FIG. 3 is a circuit diagram of a conventional input protection device. DESCRIPTION OF SYMBOLS 1... Oscillation circuit, 2... Charge pump capacitor, 3... Output end of charge pump capacitor, 4, 5... N channel transistor, 6... Reference voltage, 7... Output end of substrate bias generation circuit, 8...
Power supply, 20, 21...input protection transistor.
Claims (1)
体装置において、前記基板バイアス発生回路の出
力端子と電源端子の間に入力保護用MOSトラン
ジスタを接続し前記トランジスタの入力ゲートを
前記基板バイアス回路の出力端子に接続したこと
を特徴とする半導体入力保護装置。1. In a semiconductor device having a substrate bias generation circuit on a chip, an input protection MOS transistor is connected between the output terminal of the substrate bias generation circuit and a power supply terminal, and the input gate of the transistor is connected to the output terminal of the substrate bias circuit. A semiconductor input protection device characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62078713A JPS63244872A (en) | 1987-03-31 | 1987-03-31 | Semiconductor input protective device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62078713A JPS63244872A (en) | 1987-03-31 | 1987-03-31 | Semiconductor input protective device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63244872A JPS63244872A (en) | 1988-10-12 |
| JPH0370378B2 true JPH0370378B2 (en) | 1991-11-07 |
Family
ID=13669510
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62078713A Granted JPS63244872A (en) | 1987-03-31 | 1987-03-31 | Semiconductor input protective device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63244872A (en) |
-
1987
- 1987-03-31 JP JP62078713A patent/JPS63244872A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63244872A (en) | 1988-10-12 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term | ||
| FPAY | Renewal fee payment (event date is renewal date of database) |
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