JPH04170063A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH04170063A JPH04170063A JP29746090A JP29746090A JPH04170063A JP H04170063 A JPH04170063 A JP H04170063A JP 29746090 A JP29746090 A JP 29746090A JP 29746090 A JP29746090 A JP 29746090A JP H04170063 A JPH04170063 A JP H04170063A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- voltage
- power supply
- mos transistor
- internal circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 230000015556 catabolic process Effects 0.000 claims abstract description 13
- 230000003068 static effect Effects 0.000 abstract description 2
- 239000000758 substrate Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路に関し、特に活線挿抜可能な外
部端子の静電保護回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and more particularly to an electrostatic protection circuit for external terminals that can be hot-swappable.
従来、半導体集積回路の外部端子の静電保護回路は通常
は第5図に示すように、例えば拡散ダイオード7.8と
抵抗素子5により入力バッファ6を入力例とする内部回
路9に対して静電保護回路を構成している。Conventionally, as shown in FIG. 5, a static electricity protection circuit for an external terminal of a semiconductor integrated circuit normally protects an internal circuit 9 from which an input buffer 6 is an input using, for example, a diffusion diode 7.8 and a resistor element 5. It constitutes a power protection circuit.
しかし活線挿抜可能とするためには電源をオフした時に
、外部から供給される正電源なら゛′Hパレベル、負電
源なら“L”レベルの信号に対し電流経路を有してはい
けないので、第3図および第4図に示すように電源電位
側への(すなわち電源端子4に接続される)拡散ダイオ
ードを設けない静電保護回路を構成していた。However, in order to enable hot-line insertion and removal, when the power is turned off, there must be no current path for the signal that is at the ``H'' level if the positive power source is supplied from the outside, or is at the ``L'' level if the negative power source is supplied from the outside. As shown in FIGS. 3 and 4, an electrostatic protection circuit was configured without a diffusion diode connected to the power supply potential side (that is, connected to the power supply terminal 4).
上述した従来の活線挿抜可能な外部端子の静電保護回路
を有する半導体集積回路は、通常の静電保護回路と異な
り電源電位側への電流経路がないため、外部から外部端
子へ絶対値が電源電圧を越える過大なサージ電圧が印加
された場合に主に接地電位側へ接続された拡散ダイオー
ドがブレークダウンして電気エネルギーは基板へ放出さ
れる。The above-mentioned conventional semiconductor integrated circuit with an electrostatic protection circuit for hot-swappable external terminals differs from a normal electrostatic protection circuit in that there is no current path to the power supply potential side, so the absolute value does not change from the outside to the external terminal. When an excessive surge voltage exceeding the power supply voltage is applied, the diffusion diode mainly connected to the ground potential side breaks down and electrical energy is released to the substrate.
この時、一般にブレークダウン電圧は15V以上と高く
、このため人力バッファにおける素子にも電気エネルギ
ーが加わり易く、入力バッファの素子を破壊してしまう
ということが生じてしまい、耐破壊電圧を大きくするこ
とが困難であるという欠点があった。At this time, the breakdown voltage is generally as high as 15V or more, and therefore, electrical energy is likely to be applied to the elements in the manual buffer, causing the elements of the input buffer to be destroyed, so it is necessary to increase the breakdown voltage. The disadvantage was that it was difficult.
本発明の半導体集積回路装置は、直列抵抗を介して内部
回路の入力端に接続されるとともに、他端が接地されて
いるダイオード特性素子の一端に接続されている外部端
子を有する静電保護回路を含む半導体累積回路において
、ソース端子が電源電位点に接続されドレイン端子が前
記外部端子に接続されゲート端子が前記入力端に接続さ
れ、かつ前記内部回路の電源電圧よりも絶対値が大きく
て内部回路のダイオードのブレークダウン電圧より小さ
く設計されたしきい値電圧を有するMOSトランジスタ
を含んで構成されている。The semiconductor integrated circuit device of the present invention provides an electrostatic protection circuit having an external terminal connected to an input end of an internal circuit via a series resistor and connected to one end of a diode characteristic element whose other end is grounded. A semiconductor accumulation circuit including a source terminal connected to a power supply potential point, a drain terminal connected to the external terminal, a gate terminal connected to the input terminal, and an internal circuit whose absolute value is larger than the power supply voltage of the internal circuit. The circuit includes a MOS transistor having a threshold voltage designed to be smaller than the breakdown voltage of a diode in the circuit.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の第1の実施例の回路図である。FIG. 1 is a circuit diagram of a first embodiment of the present invention.
1はポンディングパッドへ接続される入力バッファ用の
外部端子であり、4は電源電圧5■が供給される電源端
子であり、5は抵抗素子であり、6は入力バッファであ
り、2はゲートポリシリコン直下の絶縁膜の膜厚やチャ
ネルドーピングの制御によって電源電圧5Vより大きく
ドレインと基板で構成されるダイオードのブレークダウ
ン電圧15Vより小さいしきい値電圧V↑IOVに調整
されたNチャネルトランジスタであり、トレイン端子は
直接、ゲート端子は抵抗5を介して外部端子に接続され
、ソース端子は電源端子に接続されている。また、3は
Nチャネルトランジスタ2のドレインと基板で構成され
るブレークダウン電圧15Vのダイオードである。1 is an external terminal for an input buffer connected to the bonding pad, 4 is a power supply terminal to which a power supply voltage 5 is supplied, 5 is a resistance element, 6 is an input buffer, and 2 is a gate It is an N-channel transistor whose threshold voltage V↑IOV is adjusted to be higher than the power supply voltage 5V and lower than the breakdown voltage 15V of the diode composed of the drain and substrate by controlling the thickness of the insulating film directly under the polysilicon and channel doping. The train terminal is connected directly, the gate terminal is connected to an external terminal via a resistor 5, and the source terminal is connected to a power supply terminal. Further, 3 is a diode with a breakdown voltage of 15V, which is composed of the drain of the N-channel transistor 2 and the substrate.
通常のトランジスタの酸化膜厚は0.015μmである
が、ここでは0.17μmにすると約10Vのしきい値
電圧■Tを有するトランジスタが得られる。The oxide film thickness of a normal transistor is 0.015 .mu.m, but here, by setting it to 0.17 .mu.m, a transistor having a threshold voltage (T) of about 10V can be obtained.
次に回路の動作を説明すると電源端子4に5Vが供給さ
れる使用状態では、外部端子へ論理振幅0■から5■の
信号が入力されてもNチャネルトランジスタ2はゲート
と基板間に10■を越えることはなく常にオフ状態であ
り、電源端子4が接地電位0■に短絡されたチップのオ
フ状態でも同様にNチャネルトランジスタ2はオンする
ことなく、外部端子1は活線挿抜可能である。Next, to explain the operation of the circuit, in the operating state where 5V is supplied to the power supply terminal 4, even if a signal with a logic amplitude of 0 to 5 is input to the external terminal, the N-channel transistor 2 will have a voltage of 10V between the gate and the substrate. Even in the off state of the chip where the power supply terminal 4 is short-circuited to the ground potential 0■, the N-channel transistor 2 will not turn on and the external terminal 1 can be hot-switched. .
さらに、外部端子1へ電源電圧5■を越える過大なサー
ジ電圧が印加された場合、サージ電圧が10Vを越える
とNチャネルトランジスタ2はオンし、電気エネルギー
は電源端子側へ放出され始める。Furthermore, when an excessive surge voltage exceeding the power supply voltage 5.5 is applied to the external terminal 1, when the surge voltage exceeds 10V, the N-channel transistor 2 is turned on and electrical energy begins to be released to the power supply terminal side.
これは、ダイオード3のブレークダウンにより電気エネ
ルギーを基板へ放出するより早く入力バッファ6の素子
に加わる電気エネルギーを低減することができる。This can reduce the electrical energy applied to the elements of the input buffer 6 faster than discharging electrical energy to the substrate due to the breakdown of the diode 3.
また、外部端子1へ負の過大なサージ電圧が印加された
場合は、従来と同様にダイオード3が順方向となり基板
へ容易に電気エネルギーを放出してくれる。Furthermore, when an excessively negative surge voltage is applied to the external terminal 1, the diode 3 becomes forward-directed and easily releases electrical energy to the substrate, as in the conventional case.
第2図は負電源による活線挿抜可能な外部端子における
本発明の第2の実施例の回路図である。FIG. 2 is a circuit diagram of a second embodiment of the present invention in which external terminals are hot-swappable using a negative power source.
11は電源電圧−5vが供給される電源端子であり、9
は電源電圧の絶対値5■より大きいv丁の絶対値10V
に調整されたPチャネルトランジスタであり、10はP
チャネルトランジスタ9のドレインと基板で構成される
ブレークダウン電圧15Vのダイオードである。この回
路動作特性は第1の実施例で述べたものと同様である。11 is a power supply terminal to which a power supply voltage of -5V is supplied;
is the absolute value of the power supply voltage, which is 10V, which is greater than the absolute value of the power supply voltage, which is 5■
10 is a P-channel transistor tuned to P
This is a diode with a breakdown voltage of 15V, which is composed of the drain of the channel transistor 9 and the substrate. The circuit operating characteristics are similar to those described in the first embodiment.
以上説明したように本発明の半導体累積回路は、活線挿
抜可能な外部端子において絶対値が電源電圧を越える過
大なサージ電圧が印加されたときに、ソース端子が電源
端子に接続されていて電漏電圧より絶対値が大きいしき
い値を有するM○Sトランジスタのゲート端子にしきい
値電圧と同じ電圧が加わるとともにMOS)ランジスタ
がオン状態となり、ドレイン端子より電源端子へ電気エ
ネルギーが放出される。As explained above, in the semiconductor cumulative circuit of the present invention, when an excessive surge voltage whose absolute value exceeds the power supply voltage is applied to the hot-swappable external terminal, the source terminal is connected to the power supply terminal and the When a voltage equal to the threshold voltage is applied to the gate terminal of the M○S transistor, which has a threshold value larger in absolute value than the leakage voltage, the MOS transistor is turned on, and electrical energy is released from the drain terminal to the power supply terminal.
このことにより入力バッファの素子へ加わる電気エネル
ギーが低減され破壊電圧を大きくすることができるとい
う効果がある。This has the effect of reducing the electrical energy applied to the elements of the input buffer and increasing the breakdown voltage.
第1図は本発明の第1の実施例の回路図、第2図は本発
明の第2の実施例の回路図、第3図、第4図はそれぞれ
従来の活線挿抜可能な半導体集積回路の例の回路図、第
5図は従来の半導体集積回路の他の例の回路図である。
1・・・パッド接続外部端子、2.9・・・MOS)ラ
ンジスタ(高Vt)、3.10・・・ダイオード接続M
OSトランジスタ、4.11・・・電源端子、7゜8・
・・拡散ダイオード、9・・・内部回路。FIG. 1 is a circuit diagram of a first embodiment of the present invention, FIG. 2 is a circuit diagram of a second embodiment of the present invention, and FIGS. 3 and 4 are conventional hot-swappable semiconductor integrated circuits. FIG. 5 is a circuit diagram of another example of a conventional semiconductor integrated circuit. 1... Pad connection external terminal, 2.9... MOS) transistor (high Vt), 3.10... Diode connection M
OS transistor, 4.11...power supply terminal, 7°8.
...Diffusion diode, 9...Internal circuit.
Claims (1)
もに、他端が接地されているダイオード特性素子の一端
に接続されている外部端子を有する静電保護回路を含む
半導体集積回路において、ソース端子が電源電位点に接
続されドレイン端子が前記外部端子に接続されゲート端
子が前記入力端に接続され、かつ前記内部回路の電源電
圧よりも絶対値が大きくて内部回路のダイオードのブレ
ークダウン電圧より小さく設計されたしきい値電圧を有
するMOSトランジスタを含むことを特徴とする半導体
集積回路。In a semiconductor integrated circuit including an electrostatic protection circuit having an external terminal connected to an input terminal of an internal circuit via a series resistor and connected to one end of a diode characteristic element whose other end is grounded, the source terminal is connected to a power supply potential point, a drain terminal is connected to the external terminal, a gate terminal is connected to the input terminal, and the absolute value is larger than the power supply voltage of the internal circuit and smaller than the breakdown voltage of the diode of the internal circuit. A semiconductor integrated circuit comprising a MOS transistor having a designed threshold voltage.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29746090A JPH04170063A (en) | 1990-11-02 | 1990-11-02 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29746090A JPH04170063A (en) | 1990-11-02 | 1990-11-02 | Semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04170063A true JPH04170063A (en) | 1992-06-17 |
Family
ID=17846786
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP29746090A Pending JPH04170063A (en) | 1990-11-02 | 1990-11-02 | Semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04170063A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6108186A (en) * | 1997-06-06 | 2000-08-22 | Yokoi; Akihiro | Game machine having communication terminals |
US6653693B1 (en) * | 1997-11-11 | 2003-11-25 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit device |
-
1990
- 1990-11-02 JP JP29746090A patent/JPH04170063A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6108186A (en) * | 1997-06-06 | 2000-08-22 | Yokoi; Akihiro | Game machine having communication terminals |
US6653693B1 (en) * | 1997-11-11 | 2003-11-25 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit device |
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