JPH0370379B2 - - Google Patents
Info
- Publication number
- JPH0370379B2 JPH0370379B2 JP62078714A JP7871487A JPH0370379B2 JP H0370379 B2 JPH0370379 B2 JP H0370379B2 JP 62078714 A JP62078714 A JP 62078714A JP 7871487 A JP7871487 A JP 7871487A JP H0370379 B2 JPH0370379 B2 JP H0370379B2
- Authority
- JP
- Japan
- Prior art keywords
- potential
- transistor
- input
- transistors
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 description 13
- 238000010586 diagram Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 238000005513 bias potential Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明は、半導体入力保護装置に関するもの
で、特に基板バイアスの電位が接地電位または供
給電位と異なる電位である半導体装置の入力保護
に使用されるものである。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor input protection device, and particularly to a semiconductor device in which the substrate bias potential is different from a ground potential or a supply potential. It is used for input protection.
（従来の技術）
従来の半導体入力保護装置を第２図に示す。す
なわち入力保護装置となるトランジスタＴ１およ
びＴ２のゲートは、接地６VSSに接続されており、
入力端子１１の電位が通常の動作範囲（VCC−
VSSの範囲）ならば、トランジスタＴ１およびＴ
２はカツト・オフ状態であり、本来、内部回路１
２へ影響を与えない。(Prior Art) A conventional semiconductor input protection device is shown in FIG. That is, the gates of transistors T1 and T2, which serve as input protection devices, are connected to the ground 6V SS ,
The potential of input terminal 11 is within the normal operating range (V CC −
V SS range), then transistors T1 and T
2 is the cut-off state, and originally the internal circuit 1
Does not affect 2.
仮に入力端子１１の電位が電源VCCよりも非常
に高い場合、主にトランジスタＴ１あるいはＴ２
のブレークダウン特性及びトランジスタアクシヨ
ンによつて、VSSあるいはVCCに主にトランジス
タＴ１あるいはＴ２を介して電流を流し、内部回
路１２へ高エネルギーの負担をなくす。 If the potential of the input terminal 11 is much higher than the power supply V CC , the transistor T1 or T2 will be
Due to the breakdown characteristics and transistor action, current flows to V SS or V CC mainly through transistor T1 or T2, eliminating high energy burden on internal circuitry 12.
入力端子１１の電位が接地VSSよりも非常に低
い場合には、主にMOSトランジスタＴ２あるい
はＴ１がオンして電流を流し、内部回路１２への
保護を行なう。 When the potential of the input terminal 11 is much lower than the ground V SS , the MOS transistor T2 or T1 is mainly turned on and current flows, thereby protecting the internal circuit 12.
（発明が解決しようとする問題点）
本来入力保護装置は、通常のスペツク（仕様）
範囲の条件のもとでは、トランジスタＴ１および
Ｔ２は完全にカツト・オフ状態となつて、入力端
子１１および内部回路１２に影響を与えないこと
が必要であるのに対して、温度が高いとき、保護
トランジスタのチヤンネル長が製造バラツキ上狭
くなつてしまつたとき、MOSトランジスタのし
きい値電圧Vthが低目めになつているとき等、上
記温度、チヤネル長、しきい値電圧等が許容範囲
の中にあつても、この入力保護装置のMOSトラ
ンジスタのリーク電流が増加してしまう問題をも
つている。(Problem to be solved by the invention) Originally, the input protection device had normal specifications.
Under conditions in the range, transistors T1 and T2 are required to be completely cut off and not affect the input terminal 11 and the internal circuit 12, whereas when the temperature is high, When the channel length of the protection transistor becomes narrow due to manufacturing variations, or when the threshold voltage Vth of the MOS transistor becomes relatively low, the temperature, channel length, threshold voltage, etc. mentioned above are within the allowable range. However, there is a problem in that the leakage current of the MOS transistor of this input protection device increases.
入力リーク（入力端子１１におけるリーク電
流）のスペツクがLSIでは規定されているため、
トランジスタＴ１，Ｔ２のリークがあると、なお
さら上記スペツクを満足しにくくなる。 Since the specifications for input leakage (leakage current at input terminal 11) are specified in LSI,
If there is leakage from the transistors T1 and T2, it becomes even more difficult to satisfy the above specifications.
又、スペツクを満足するため、保護トランジス
タＴ１およびＴ２のチヤンネル長をあらかじめ大
きく設定しておくと、本来の目的である保護とし
ての役割不足になつてしまう。 Furthermore, if the channel lengths of the protection transistors T1 and T2 are set large in advance in order to satisfy the specifications, they will not be able to fulfill their original purpose of protection.
本発明は、入力保護装置によつて入力特性を変
えることなく、入力保護を行なうことを目的とす
る。 An object of the present invention is to perform input protection without changing input characteristics using an input protection device.
（問題点を解決するための手段と作用）
本発明は、第１の電位と第２の電位の間で動作
する半導体装置において、入力端子と前記第１の
電位あるいは第２の電位との間に１個以上のトラ
ンジスタが接続され、かつ前記トランジスタの入
力ゲート端に第３の電位が接続され、前記第３の
電位は、前記第１の電位と第２の電位の間の範囲
外にあり、通常動作時は前記トランジスタをカツ
ト・オフ状態にせしめ、前記入力端子に前記範囲
外の電圧が印加されたとき前記トランジスタに電
流を流すことを特徴とする半導体入力保護装置で
ある。即ち例えば入力保護用トランジスタがＮチ
ヤンネルの場合、そのトランジスタＴ１及びＴ２
の入力ゲートに、接地電位よりも低い電位VBBを
供給し、通常動作時にはＴ１，Ｔ２を完全にカツ
トオフ状態とし、入力リーク電流等のLSIの諸特
性に影響をおよぼさないようにした回路である。
なお、通常のNMOS LSIではマイナス電位発生
回路を内蔵して動作スピードのアツプ化をはかつ
ており、上記保護回路のために、上記マイナス電
位発生回路を準備する必要はない。
(Means and Effects for Solving the Problems) The present invention provides a semiconductor device that operates between a first potential and a second potential. one or more transistors are connected to the transistor, and a third potential is connected to the input gate end of the transistor, and the third potential is outside the range between the first potential and the second potential. , a semiconductor input protection device characterized in that the transistor is cut off during normal operation, and current flows through the transistor when a voltage outside the range is applied to the input terminal. That is, for example, if the input protection transistor is an N-channel transistor, the transistors T1 and T2
A circuit that supplies a potential V BB lower than the ground potential to the input gate of the circuit, and completely cuts off T1 and T2 during normal operation to prevent input leakage current and other characteristics of the LSI from being affected. It is.
Note that a normal NMOS LSI has a built-in negative potential generation circuit to increase its operating speed, so there is no need to prepare the negative potential generation circuit for the protection circuit.
（実施例）
以下図面を参照して本発明の一実施例を説明す
る。第１図は同実施例の回路図であるが、これは
前記のものと対応させた場合の例であるから、対
応個所には同一符号を用いる。ここで基板バイア
ス発生回路２１は、Ｎチヤンネル・トランジスタ
の場合、基準電位VSSより低い電位を基板バイア
スとして与えるものであり、多くの製品に使用さ
れている。第１図に示す基板バイアス発生回路２
１はその一例を示す。即ち発振回路１の出力を、
増幅器９を介してチヤージ・ポンプ・キヤパシタ
２の入力端に接続する。前記チヤージ・ポンプ・
キヤパシタ２の出力端３を、第１のトランジスタ
４の２端子および第２のトランジスタ５の１端子
に接続し、第１のトランジスタ４の他の１端子を
基準電位６に接続し、第２のトランジスタ５の別
の２端子を基板バイアス発生回路の出力端７に接
続する。(Example) An example of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of the same embodiment, but since this is an example in which the circuit corresponds to the one described above, the same reference numerals are used for corresponding parts. Here, in the case of an N-channel transistor, the substrate bias generation circuit 21 provides a potential lower than the reference potential V SS as a substrate bias, and is used in many products. Substrate bias generation circuit 2 shown in FIG.
1 shows an example. That is, the output of the oscillation circuit 1 is
It is connected to the input end of the charge pump capacitor 2 via an amplifier 9. The charge pump
The output end 3 of the capacitor 2 is connected to two terminals of the first transistor 4 and one terminal of the second transistor 5, the other one terminal of the first transistor 4 is connected to the reference potential 6, and the second The other two terminals of transistor 5 are connected to output terminal 7 of the substrate bias generation circuit.
すなわち、前記発振回路１によつて発生した連
続パルスを、前記キヤパシタ２によつて前記出力
端３を遷移させる。前記出力端３の電位が前記基
準電位６よりも高くなつた場合、前記第１のトラ
ンジスタ４がオン状態になり、前記基準電位６に
電流を流し、前記出力端３の電位を前記基準電位
にする。逆に、前記出力端３の電位が前記基準電
位６よりも低い場合、前記第１のトランジスタ４
はオフ状態になり、前記出力端３の電位を保持す
る。 That is, the continuous pulses generated by the oscillation circuit 1 are caused to transition at the output terminal 3 by the capacitor 2. When the potential of the output terminal 3 becomes higher than the reference potential 6, the first transistor 4 is turned on and current flows through the reference potential 6, causing the potential of the output terminal 3 to reach the reference potential. do. Conversely, when the potential of the output terminal 3 is lower than the reference potential 6, the first transistor 4
turns off and holds the potential at the output terminal 3.
次に、前記基板バイアス発生回路の出力端７の
電位が前記出力端３より高い場合、前記第２のト
ランジスタ５がオン状態になり、前記基板バイア
ス出力端７の電位を、前記出力端３の電位にす
る。逆に、前記基板バイアス出力端７の電位が前
記出力端３よりも低い場合、前記第２のトランジ
スタ５はオフ状態になり、前記基板バイアス出力
端７の電位を保持する。 Next, when the potential of the output terminal 7 of the substrate bias generation circuit is higher than the output terminal 3, the second transistor 5 is turned on, and the potential of the substrate bias output terminal 7 is changed to the potential of the output terminal 3. potential. Conversely, when the potential of the substrate bias output terminal 7 is lower than that of the output terminal 3, the second transistor 5 is turned off and the potential of the substrate bias output terminal 7 is maintained.
以上のようにして、前記基板バイアス回路出力
端子７の電位はマイナス電位VBBに保持される。 As described above, the potential of the substrate bias circuit output terminal 7 is held at the negative potential VBB .
しかして上記ＮチヤンネルトランジスタＴ１お
よびＴ２の入力ゲートをVSSよりも低い電位の
VBBと接続することによつて、通常の動作電位範
囲においては、トランジスタＴ１およびＴ２のゲ
ートーソース間電位をマイナス電位になるように
して、トランジスタＴ１およびＴ２をリーク電流
のない完全なカツト・オフ状態にする。 Therefore, the input gates of the N-channel transistors T1 and T2 are at a potential lower than V SS .
By connecting to V BB , the gate-source potential of transistors T1 and T2 becomes a negative potential in the normal operating potential range, and transistors T1 and T2 are completely cut off with no leakage current. Make it.
入力端子１１の電位が電源VCCよりも非常に高
い場合は、トランジスタＴ１またはＴ２のブレー
クダウン特性及びトランジスタアクシヨンによつ
て、VSSまたはVCCにトランジスタを介して電流
を流し、内部回路１２へ高エネルギーを与えず吸
収する。 When the potential of the input terminal 11 is much higher than the power supply V CC , the breakdown characteristics and transistor action of the transistor T1 or T2 cause a current to flow to V SS or V CC through the transistor, and the internal circuit 12 Absorbs high energy without giving it to.
又、入力端子１１の電位がVSSより非常に低い
場合には、MOSトランジスタＴ１，Ｔ２が動作
して電流を流し、内部回路１２の保護をする。基
板バイアス発生回路（マイナス電位VBB発生）２
１は通常のNMOS LSIでは具備されており、基
板電位をマイナスにすることにより、拡散容量を
下げて動作スピードの向上をはかつている。その
ため、この入力保護装置のマナス電位供給に対し
て、あらたに準備するものではない。 Furthermore, when the potential of the input terminal 11 is much lower than V SS , the MOS transistors T1 and T2 operate to flow current and protect the internal circuit 12. Substrate bias generation circuit (minus potential V BB generation) 2
1 is provided in a normal NMOS LSI, and by making the substrate potential negative, the diffusion capacitance is lowered and the operation speed is improved. Therefore, no new preparations are made for the supply of manas potential to this input protection device.
なお本発明は実施例のみに限られることなく
種々の応用が可能である。例えば実施例では、入
力保護トランジスタＴ１，Ｔ２をＮチヤンネルと
したが、Ｐチヤンネルを用いた基板バイアス発生
回路の場合、トランジスタＴ１，Ｔ２をＰチヤン
ネルMOSトランジスタとすることもできる。ま
た本発明にあつてはトランジスタＴ１，Ｔ２のち
いずれか一方を用いる場合にも適用できる。 Note that the present invention is not limited to the embodiments, and can be applied in various ways. For example, in the embodiment, the input protection transistors T1 and T2 are N-channel, but in the case of a substrate bias generation circuit using a P-channel, the transistors T1 and T2 may be P-channel MOS transistors. Furthermore, the present invention can also be applied to the case where either one of the transistors T1 and T2 is used.
従来の保護回路方式であると保護回路としての
役割は果たすが、温度条件が厳しくなつた場合、
保護トランジスタのチヤンネル幅が狭くなつたと
き、MOSトランジスタのしきい値電圧が低目で
あるとき等、動作条件がスペツクの範囲内であつ
ても入力のリーク電流が増加してしまい、この入
力リークスペツクをクリアー出来なくなつてしま
う。
The conventional protection circuit method fulfills its role as a protection circuit, but when the temperature conditions become severe,
When the channel width of the protection transistor becomes narrow, or when the threshold voltage of the MOS transistor is low, the input leakage current increases even if the operating conditions are within the specification range. I end up not being able to clear it.
これに対し、本発明は保護トランジスタのゲー
ト電極に、マイナス電位（ＮチヤンネルMOSト
ランジスタの場合）またはVSS電位より高い電位
（ＰチヤンネルMOSトランジスタの場合）を供給
することにより、通常の動作時において、まつた
く諸特性に影響をおよぼさない利点をもつた入力
保護装置である。 In contrast, the present invention provides a negative potential (in the case of an N-channel MOS transistor) or a potential higher than the V SS potential (in the case of a P-channel MOS transistor) to the gate electrode of the protection transistor. This input protection device has the advantage of not affecting various characteristics.
第１図は本発明の一実施例を示す回路図、第２
図は従来装置の回路図である。
１１…入力端子、１２…内部回路、２１…マイ
ナス電位発生回路、Ｔ１，Ｔ２…入力保護トラン
ジスタ。
Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure is a circuit diagram of a conventional device. DESCRIPTION OF SYMBOLS 11...Input terminal, 12...Internal circuit, 21...Minus potential generation circuit, T1, T2...Input protection transistor.
Claims (1)
体装置において、入力端子と前記第１の電位ある
いは第２の電位との間に１個以上のトランジスタ
が接続され、かつ前記トランジスタの入力ゲート
端に第３の電位が接続され、前記第３の電位は、
前記第１の電位と第２の電位の間の範囲外にあ
り、通常動作時は前記トランジスタをカツト・オ
フ状態にせしめ、前記入力端子に前記範囲外の電
圧が印加されたとき前記トランジスタに電流を流
すことを特徴とする半導体入力保護装置。1 In a semiconductor device that operates between a first potential and a second potential, one or more transistors are connected between an input terminal and the first potential or the second potential, and the input terminal of the transistor is A third potential is connected to the gate end, and the third potential is
outside the range between the first potential and the second potential, causing the transistor to be cut off during normal operation, and causing a current to flow through the transistor when a voltage outside the range is applied to the input terminal. A semiconductor input protection device characterized by flowing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62078714A JPS63244873A (en) | 1987-03-31 | 1987-03-31 | Semiconductor input protective device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62078714A JPS63244873A (en) | 1987-03-31 | 1987-03-31 | Semiconductor input protective device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63244873A JPS63244873A (en) | 1988-10-12 |
| JPH0370379B2 true JPH0370379B2 (en) | 1991-11-07 |
Family
ID=13669539
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62078714A Granted JPS63244873A (en) | 1987-03-31 | 1987-03-31 | Semiconductor input protective device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63244873A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2754072B2 (en) * | 1990-02-07 | 1998-05-20 | 三菱電機株式会社 | Input circuit of semiconductor device |
-
1987
- 1987-03-31 JP JP62078714A patent/JPS63244873A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63244873A (en) | 1988-10-12 |
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