JPH0370146A - 回路基板の製造方法 - Google Patents

回路基板の製造方法

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Publication number
JPH0370146A
JPH0370146A JP1206480A JP20648089A JPH0370146A JP H0370146 A JPH0370146 A JP H0370146A JP 1206480 A JP1206480 A JP 1206480A JP 20648089 A JP20648089 A JP 20648089A JP H0370146 A JPH0370146 A JP H0370146A
Authority
JP
Japan
Prior art keywords
solder resist
wire bonding
resist layer
bonding pad
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1206480A
Other languages
English (en)
Inventor
Mutsusada Itou
睦禎 伊藤
Katsuya Kosuge
小菅　克也
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP1206480A priority Critical patent/JPH0370146A/ja
Publication of JPH0370146A publication Critical patent/JPH0370146A/ja
Pending legal-status Critical Current

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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、回路基板の製造方法に関し、更に詳しくは、
回路部品を良好に実装できるチップオンボートタイプの
回路基板の製造方法に係わる。
ｒ発明の概要］ 本発明は、第１の半田レジスト層が形成された回路基板
上の、ワイヤボンディングパッド部を覆って第１の半田
レジストとはエツチング特性の異なる第２の半田レジス
ト層を形成する工程と、前記回路基板に回路部品を半田
リフローにより半田付けする工程と、 前記第２の半田レジスト層を除去する工程と、ワイヤボ
ンディング工程とを具備することにより、 ワイヤボンディングパッド部に半田が付着することがな
く、ボンディング面の清浄を保ち、しかも、ワイヤボン
ディングパッド部と部品ランドの間隔を小さくすること
が可能な回路基板の製造方法を得んとするものである。
［従来の技術］ 従来、この種の回路基板としては、第２図に示すような
ものが知られている。このような回路基板の製造方法と
しては、先ず、表面に絶縁樹脂が被覆された基板ｌ上に
銅系の導電ペーストを印刷してワイヤボンディングパッ
ド部２．配線パターン３９部品ランド部４等を形成する
。次に、回路部品５を部品ランド部４上に載置した後、
リフローを行い半田付け６を施し、その後回路部品５と
ワイヤボンディングパッド２の間にワイヤボンディング
を行い、ボンディングワイヤ７を配線する。
［発明が解決しようとする課題］ しかしながら、このような従来の回路基板の製造方法に
あっては、半田付けを行う際に、ワイヤボンディングパ
ッド部２上に半田６ａが飛び散り、ともするとワイヤボ
ンディング不良の原因となっていた。
また、このような半田の飛び散りが起こるため、ワイヤ
ボンディングパッド部２と部品ランド部４との間隔を大
きくとらなければならない問題点があった。
本発明は、このような従来の問題点に着目して創案され
たものであって不良率が低く、しかもモジュールの小型
化を可能にする回路基板の製造方法を得んとするもので
ある。
［課題を解決するための手段］ そこで、本発明は、第１の半田レジスト層が形成された
回路基板上の、ワイヤボンディングパッド部を覆って第
１の半田レジストとはエツチング特性の異なる第２の半
田レジスト層を形成する工程と、 １γｊ記回路基板に回路部品を半田リフローにより半田
付けする工程と、 前記第２の半田レジスト層を除去する工程と、ワイヤボ
ンディング工程とを具備することを、その解決手段とし
ている。
［作用］ ワイヤボンディングパッド部を、第１の半田レジストと
はエツチング特性の異なる第２の半田レジスト層で覆っ
たことにより、半田付は工程により半田が第２の半田レ
ジスト層上に付着しても、後の第２の半田レジスト層の
除去工程により、付着した半田も一緒に除去されるため
ワイヤボンディングパッド部の清浄が確保される。また
、半田以外の汚染に対しても同様の作用を有する。
［実施例］ 以下、本発明に係る回路基板の製造方法の詳細を図面に
示す実施例に基づいて説明する。
第１図Ａ〜第１図りは、本発明の実施例を示す断面図で
ある。
先ず、本実施例は、第１図Ａに示すように、例えば、ア
ルミ板上に絶縁樹脂をコーティングしてなる基板１０に
、銅系の導電ペーストを印刷して所定の配線１１．ワイ
ヤボンディングパッド部１２、部品ランド部１３等を形
成し、次に、これら配線１１．ワイヤボンディングパッ
ド部１２．部品ランド部１３等の間の領域に第１の半田
レジストとしての第１ソルダレジスト層１４を形成する
。
次に、第１図Ｂに示すように、ワイヤボンディングパッ
ド部！２表面に、第２の半田レジストとしての第２ソル
ダレジスト層Ｉ５を被覆する。この第２ソルダレジスト
層１５は、第１ソルダレジスト層１４に比べて選択比を
有するようになっている。
次いで、第１図Ｃに示すように、所定箇所に半田印刷を
施し、部品ランド１３上に回路部品Ｉ６を載置し、リフ
【１−法により半田付けを行う。同図Ｃ中１７は、半田
付けされた半田であり、１７ａは第２ソルダレジスト層
！４上に飛び散った半田を示している。
次に、第２ソルダレジスト層１５をフッ素又は塩素系溶
済で洗浄して除去する。
その後、通常のワイヤボンディングを行い、第１図りに
示すように、回路部品１６とワイヤボンディングパッド
部１２とをボンディングワイヤ７で接続すればよい。
以上、実施例について説明したが、本発明はこの他に各
種の設計変更が可能であり、例えば上記実施例において
は半田付けをリフロー法によって行ったが、浸漬半田付
は法等を用いても勿論よい。
また、上記実施例においては回路部品１６を載置する部
品ランド部Ｉ３を形成したが、他のマウント方式を選択
した場合にも、本発明を適用出来ることは言うまでもな
い。
ト層、 部品、 ３・・・部品ランド、１４・・・第１ソルダレジス１５
・・・第２ソルダレジスト層、１６・・・回路１７．１
７ａ・・・半田。
［発明の効果］ 以上の説明から明らかなように、本発明に係る回路基板
の製造方法によれば、ワイヤボンディングパッド部に半
田が付着することがなく、回路不良を減少させる効果が
ある。
また、ワイヤボンディングパッド部への半田付着が防止
出来るため、回路部品とワイヤボンディングパッド部の
間隔を小さく出来、モジュールの小型化を達成出来る効
果がある。
さらに、半田以外の汚染に対しても、ワイヤボンディン
グ面を清浄に保護する効果がある。
【図面の簡単な説明】
第１図Ａ〜第１図りは本発明に係る回路基板の製造方法
の実施例の各工程を示す断面図、第２図は従来例の断面
図である。 ＩＯ・・・基板、１２・・・ワイヤボンディングパッド
外Ｉ名 （矢 方色Ａ列） （大　方乞θｌＪ） 第１図Ｂ （矢尻Ａり１（） 第１図Ｄ

Claims (1)

    【特許請求の範囲】
  1. （１）第１の半田レジスト層が形成された回路基板上の
    、ワイヤボンディングパッド部を覆って第１の半田レジ
    ストとはエッチング特性の異なる第２の半田レジスト層
    を形成する工程と、 前記回路基板に回路部品を半田リフローにより半田付け
    する工程と、 前記第２の半田レジスト層を除去する工程と、ワイヤボ
    ンディング工程とを具備することを特徴とする回路基板
    の製造方法。
JP1206480A 1989-08-09 1989-08-09 回路基板の製造方法 Pending JPH0370146A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1206480A JPH0370146A (ja) 1989-08-09 1989-08-09 回路基板の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1206480A JPH0370146A (ja) 1989-08-09 1989-08-09 回路基板の製造方法

Publications (1)

Publication Number Publication Date
JPH0370146A true JPH0370146A (ja) 1991-03-26

Family

ID=16524074

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1206480A Pending JPH0370146A (ja) 1989-08-09 1989-08-09 回路基板の製造方法

Country Status (1)

Country Link
JP (1) JPH0370146A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09293744A (ja) * 1996-02-29 1997-11-11 Denso Corp 電子部品の実装方法
JP2007335782A (ja) * 2006-06-19 2007-12-27 Fuji Electric Fa Components & Systems Co Ltd 半導体装置モジュールの製造方法及び半導体装置モジュール

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09293744A (ja) * 1996-02-29 1997-11-11 Denso Corp 電子部品の実装方法
JP2007335782A (ja) * 2006-06-19 2007-12-27 Fuji Electric Fa Components & Systems Co Ltd 半導体装置モジュールの製造方法及び半導体装置モジュール

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