JPH0364056A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0364056A JPH0364056A JP1200516A JP20051689A JPH0364056A JP H0364056 A JPH0364056 A JP H0364056A JP 1200516 A JP1200516 A JP 1200516A JP 20051689 A JP20051689 A JP 20051689A JP H0364056 A JPH0364056 A JP H0364056A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- semiconductor device
- die
- view
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 19
- 238000000034 method Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 238000000465 moulding Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 abstract description 12
- 239000000853 adhesive Substances 0.000 abstract description 11
- 230000001070 adhesive effect Effects 0.000 abstract description 11
- 238000009434 installation Methods 0.000 abstract 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 238000003754 machining Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000011109 contamination Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 229920002379 silicone rubber Polymers 0.000 description 1
- 239000004945 silicone rubber Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は中空パ・１ケージ等の半導体装置の構造に関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a semiconductor device such as a hollow package.
第４図は従来の中空パ・ソケージの半導体装置の圧力セ
ンサーの場合のパ・ソケージ構造を示す断面側面図、第
５図は第４図のパッケージを製造するフローチャートを
示す。FIG. 4 is a sectional side view showing a conventional hollow package structure for a pressure sensor of a semiconductor device, and FIG. 5 is a flowchart for manufacturing the package of FIG. 4.
図において、（１）はリードフレーム、（２）は半導体
素子とリードフレームを接続するシリコン樹脂等のダイ
ボンド材、（４）は金線等のワイヤボンディング材、（
５）はベース、（６）はキヤ・ソプ、（７）はパ・ソケ
ージを作成する際にベース（５）とキヤ・ソプ（６）を
接着スるエポキシ樹脂等の接着剤である。In the figure, (1) is a lead frame, (2) is a die bonding material such as silicone resin that connects the semiconductor element and the lead frame, (4) is a wire bonding material such as gold wire, (
5) is a base, (6) is a cover, and (7) is an adhesive such as epoxy resin that is used to bond the base (5) and the cover (6) when making a pass cage.
次に動作について説明する。Next, the operation will be explained.
従来の圧力センサーＩＣは第６図（ｍｌ−（６）の工程
図に示す様に、リードフレーム（１）に半導体素子（３
）をシリコンゴム等のダイボンド材Ｏを用いてダイボン
ドしく（ａ）図）、金線（４）等によってワイヤボンド
した後（（ｂ）図）、ベースク５）とキヤ・ソプ（６）
をエポキシ樹脂等の接着剤（７）を用いて接着固定させ
て完゛成する（（６）図）。As shown in the process diagram in Figure 6 (ml-(6)), a conventional pressure sensor IC has a semiconductor element (3
) is die-bonded using a die-bonding material O such as silicone rubber (Fig. (a)), and wire-bonded with gold wire (4) etc. (Fig. (b)).
is completed by adhering and fixing using an adhesive (7) such as epoxy resin (Figure (6)).
また、第７図（ａ）はエッチング法等によって作られた
従来のリードフレームの平面図、第７図ω）は第７図（
＆）の側面図である。図中、（１ａ）はリードフレーム
（１）のうち、半導体素子（３）との接続を行う金線（
４）が接続する部分で、インナーリード（１ｂ）はリー
ドフレーム（１）のうち、半導体素子（３）をダイボン
ドするダイパ゛ソトである。Also, FIG. 7(a) is a plan view of a conventional lead frame made by etching method etc., and FIG. 7(ω) is a plan view of a conventional lead frame made by etching method etc.
&) is a side view. In the figure, (1a) is a gold wire (of the lead frame (1)) that connects with the semiconductor element (3).
4), the inner lead (1b) is a die conductor for die-bonding the semiconductor element (3) of the lead frame (1).
従来のリードフレームはインナーリード及びダィパ゛ソ
トの高さが同じで平担のため、第８図に示す様にダイボ
ンド材（２）又はキャップ（６）とベース（５）の接着
剤（７）がワイヤボンドエリアに流れ出し、ステ・ソチ
部のボンディング性を悪くするという問題点があった。In conventional lead frames, the inner leads and the die plate are flat with the same height, so as shown in Figure 8, the die bonding material (2) or the adhesive (7) between the cap (6) and the base (5) is used. There was a problem in that this flowed out into the wire bond area, impairing the bonding properties of the station and sochi parts.
第７図（ａ）はダイボンド材のしみ出した場合を示す。FIG. 7(a) shows a case where the die-bonding material seeps out.
第７図（ｂｌは接着剤のしみ出した場合を示す。FIG. 7 (bl shows the case where the adhesive oozes out).
この発明は上記のような問題点を解消するためになされ
たもので、ワイヤボンドエリアの汚染防止を図った半導
体装置を得ることを目的とする。The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor device in which contamination of the wire bond area is prevented.
この発明に係る半導体装置は、リードフレームを工・ソ
チング法によってエツチング凹部を設けたものである。In the semiconductor device according to the present invention, an etching recess is provided in a lead frame by a machining/sawching method.
〔作用〕
この発明におけるリードフレームのワイヤボンドエリア
以外に設けたリードフレームの工・ソチング凹部により
、ワイヤボンドエリアの汚染が防止され、確実にワイヤ
ボンドがなされ、信頼性の向上が計られる。[Function] In the present invention, the lead frame machining/sawching recess provided outside the wire bond area of the lead frame prevents contamination of the wire bond area, ensures wire bonding, and improves reliability.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図（ａ）はこの発明の一実施例であるリードフレー
ムの平面図、第１図（ｂ）は第１図（＆）の部分拡大断
面図である。なお１図中符号（１）から（７）までは前
記従来のものと同一につき説明を省略する。図において
、（８）はリードフレーム（１）のインナーリード部（
］０及びダイパッド部（Ｉｂ）の１部を工・ソチングし
てできた凹部である。FIG. 1(a) is a plan view of a lead frame which is an embodiment of the present invention, and FIG. 1(b) is a partially enlarged sectional view of FIG. 1(&). Note that symbols (1) to (7) in FIG. 1 are the same as those of the conventional device, so explanations thereof will be omitted. In the figure, (8) is the inner lead part (
] 0 and a part of the die pad portion (Ib) by machining and sawching.
第３図はこの発明の半導体装置の全体構成図である。FIG. 3 is an overall configuration diagram of the semiconductor device of the present invention.
第２図はこの発明の一実施例によるリードフレームを用
いた半導体装置の部分断面図である。FIG. 2 is a partial sectional view of a semiconductor device using a lead frame according to an embodiment of the present invention.
次に動作について説明する。Next, the operation will be explained.
第２図に示す様に、リードフレーム（１）のダイパ・ソ
ト（ｌｂ）の一部が凹部（８〉になっている為、ダイボ
ンド材（２）の流れ込みが無く又、インナーリード（１
）の一部に凹部（８）を設ける事により外部の接着剤（
７）が流れ込まない。従って、確実なワイヤボンディン
グができる。As shown in Fig. 2, a part of the die pad (lb) of the lead frame (1) is a recess (8>), so the die bonding material (2) does not flow into the inner lead (1).
) by providing a recess (8) in a part of the external adhesive (
7) does not flow. Therefore, reliable wire bonding can be performed.
なお、上記実施例では半導体装置のリードフレーム構造
を示したが、金型成形による凹部を設けてもよく、上記
実施例と同様の効果を奏する。Although the lead frame structure of the semiconductor device is shown in the above embodiment, a concave portion may be formed by molding, and the same effect as in the above embodiment can be obtained.
以上のようにこの発明によれば、リードフレームの一部
をダイボンド材又は接着剤面より低くした凹部を設けた
ので、ダイボンド材または接着剤の流れ出しによるワイ
ヤボンド不良が無くなり、信頼性の高い半導体装置が得
られる効果がある。As described above, according to the present invention, a part of the lead frame is provided with a recess that is lower than the surface of the die bonding material or adhesive, which eliminates wire bonding defects caused by the die bonding material or adhesive flowing out, and provides highly reliable semiconductors. There is an effect that the device can obtain.
第１図（ａｌはこの発明の一実施例を示す半導体装置の
リードフレームの平面図、第１図（１１）は第１図（ｍ
ｌの部分拡大断面図、第２図はこの発明の一実施例であ
る半導体素子実装の状態を示す断面図、第３図はこの発
明の一実施例である半導体装置のパッケージ構造を示す
断面図、第４図は従来の中空パッケージ構造の断面側面
図、第５図は第４図の中空パッケージ（圧力センサー）
の製造工程のフローチャート、第６図（ａ）〜（１）は
第４図の中空パ・ソケージの製造工程を示す断面図、第
７図（ａ） （ｂ）は従来のリードフレームの平面図お
よび部分拡大断面図、第８図は従来のリードフレームの
問題点を示した説明図である。
図ニオイて、（１）はリードフレーム、（１ｍ）１．ｔ
インナリード、（１ｂ）はダイパッド部、（２）はダ
イボンド材、（３）は半導体素子、（４）は金線、（５
）はベース、（６）はキャップ、（７〉は接着剤、（８
）は工・ソチング凹部ヲ示ス。
なお、図中、同一符号は同一、又は相当部分を示す。FIG. 1 (al is a plan view of a lead frame of a semiconductor device showing one embodiment of the present invention, FIG. 1 (11) is a plan view of a lead frame of a semiconductor device showing one embodiment of the present invention
FIG. 2 is a cross-sectional view showing a semiconductor device mounting state according to an embodiment of the present invention, and FIG. 3 is a cross-sectional view showing a package structure of a semiconductor device according to an embodiment of the present invention. , Figure 4 is a cross-sectional side view of the conventional hollow package structure, and Figure 5 is the hollow package (pressure sensor) of Figure 4.
6(a) to (1) are cross-sectional views showing the manufacturing process of the hollow package shown in FIG. 4, and FIGS. 7(a) and 7(b) are plan views of the conventional lead frame. and a partially enlarged cross-sectional view, and FIG. 8 is an explanatory view showing problems of the conventional lead frame. As shown in the figure, (1) is a lead frame, (1m) 1. t
Inner lead, (1b) is die pad part, (2) is die bonding material, (3) is semiconductor element, (4) is gold wire, (5
) is the base, (6) is the cap, (7> is the adhesive, (8
) indicates the machining/soching recess. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
ド部の一部をエッチング法によるハーフエッチングを施
こすか又は金型成形による凹状部を設けた事を特徴とす
る半導体装置。A semiconductor device characterized in that a part of a bonding pad portion and an inner lead portion of a lead frame is half-etched by an etching method or a recessed portion is provided by molding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1200516A JPH0364056A (en) | 1989-08-01 | 1989-08-01 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1200516A JPH0364056A (en) | 1989-08-01 | 1989-08-01 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0364056A true JPH0364056A (en) | 1991-03-19 |
Family
ID=16425614
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1200516A Pending JPH0364056A (en) | 1989-08-01 | 1989-08-01 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0364056A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7256504B2 (en) | 2004-04-06 | 2007-08-14 | Siemens Aktiengesellschaft | Circuit support for a semiconductor chip and component |
-
1989
- 1989-08-01 JP JP1200516A patent/JPH0364056A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7256504B2 (en) | 2004-04-06 | 2007-08-14 | Siemens Aktiengesellschaft | Circuit support for a semiconductor chip and component |
| DE102004016940B4 (en) | 2004-04-06 | 2019-08-08 | Continental Automotive Gmbh | Circuit carrier for a semiconductor chip and a component with a semiconductor chip |
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