JPH0363251U - - Google Patents
Info
- Publication number
- JPH0363251U JPH0363251U JP12471789U JP12471789U JPH0363251U JP H0363251 U JPH0363251 U JP H0363251U JP 12471789 U JP12471789 U JP 12471789U JP 12471789 U JP12471789 U JP 12471789U JP H0363251 U JPH0363251 U JP H0363251U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- address
- register
- registers
- cache memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
- 239000003607 modifier Substances 0.000 description 2
Description
第１図は、この考案の一実施例によるメモリ制
御装置を示す図、第２図は従来のメモリ制御装置
を示す図、第３図は従来の装置で特に問題となる
ような、メモリの使い方の例である。
図において、１は論理アドレス、２はオフセツ
ト、３はエリア番号、４はデイレクトメモリ、５
はモデイフアイビツト、６はバリツドビツト、７
はキヤツシユ、８はベースレジスタ、９はサイズ
レジスタ、１０はＡＮＤ回路、１１は加算器であ
る。なお、図中、同一符号は同一または相当部分
を示す。
FIG. 1 is a diagram showing a memory control device according to an embodiment of this invention, FIG. 2 is a diagram showing a conventional memory control device, and FIG. 3 is a diagram showing how to use memory, which is a particular problem in the conventional device. This is an example. In the figure, 1 is a logical address, 2 is an offset, 3 is an area number, 4 is a direct memory, and 5 is a
is the modifier bit, 6 is the variable bit, 7 is the modifier bit,
is a cache, 8 is a base register, 9 is a size register, 10 is an AND circuit, and 11 is an adder. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
、アドレスオフセツト値を保持するレジスタ、ア
ドレス範囲を指定するレジスタの２つのレジスタ
を複数組持ち、これらのレジスタの値によりメモ
リアドレスから対応するキヤツシユメモリのアド
レス値を求めることを特徴とするメモリ制御装置
。 A memory device equipped with a cache memory has multiple sets of two registers: a register that holds an address offset value and a register that specifies an address range, and the values of these registers are used to determine the corresponding cache memory address from a memory address. A memory control device characterized by determining a value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12471789U JPH0363251U (en) | 1989-10-25 | 1989-10-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12471789U JPH0363251U (en) | 1989-10-25 | 1989-10-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0363251U true JPH0363251U (en) | 1991-06-20 |
Family
ID=31672622
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12471789U Pending JPH0363251U (en) | 1989-10-25 | 1989-10-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0363251U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008081895A (en) * | 2006-09-28 | 2008-04-10 | Daio Paper Corp | Disposable glove |
-
1989
- 1989-10-25 JP JP12471789U patent/JPH0363251U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008081895A (en) * | 2006-09-28 | 2008-04-10 | Daio Paper Corp | Disposable glove |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0363251U (en) | ||
| JPH02143603U (en) | ||
| JPS6343563Y2 (en) | ||
| JPS5562576A (en) | Information processing unit with address conversion function | |
| JPH0370652U (en) | ||
| JPH0433156U (en) | ||
| JPS6087050U (en) | data transfer control device | |
| JPH039004U (en) | ||
| JPS60126846U (en) | Memory switching control circuit | |
| JPH03119238U (en) | ||
| JPH0295456U (en) | ||
| JPH0289556U (en) | ||
| JPH0473249U (en) | ||
| JPH01120250U (en) | ||
| JPS6457536U (en) | ||
| JPH0270249U (en) | ||
| JPH0296697U (en) | ||
| JPH0482728U (en) | ||
| JPS6131303U (en) | A hair dryer that automatically alternates between hot and cold air. | |
| JPH0284949U (en) | ||
| JPS58129554U (en) | Data processing device with memory map type I/O | |
| JPH01127048U (en) | ||
| JPH02138356U (en) | ||
| JPH0426500U (en) | ||
| JPH02291036A (en) | Memory control circuit |