JPH0295456U - - Google Patents
Info
- Publication number
- JPH0295456U JPH0295456U JP354089U JP354089U JPH0295456U JP H0295456 U JPH0295456 U JP H0295456U JP 354089 U JP354089 U JP 354089U JP 354089 U JP354089 U JP 354089U JP H0295456 U JPH0295456 U JP H0295456U
- Authority
- JP
- Japan
- Prior art keywords
- bus
- buses
- receiver
- dual port
- port memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000009977 dual effect Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Bus Control (AREA)
Description
第１図及び第２図は本考案の１実施例を示す複
数のバスに対応するインターフエースボードのブ
ロツク図である。
１……バスインターフエース部、２……スリー
ステートバツフア（バストランスミツタ／レシー
バ）、３……アドレスデコーダ、４……デユアル
ポートメモリ。
FIGS. 1 and 2 are block diagrams of an interface board that supports multiple buses, showing one embodiment of the present invention. 1... Bus interface section, 2... Three-state buffer (bus transmitter/receiver), 3... Address decoder, 4... Dual port memory.
Claims (1)
ア（バストランスミツタ／レシーバ）を設けたバ
スインターフーイス回路を具備し、異種バス間、
同種バス間の接続、及び複数のＣＰＵから使用す
るバスの選択を可能にしたことを特徴とする複数
バスに対応するインターフエースボード。 Equipped with a bus interface circuit with dual port memory and three-state buffer (bus transmitter/receiver),
An interface board compatible with multiple buses, characterized in that it enables connection between buses of the same type and selection of a bus to be used from multiple CPUs.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP354089U JPH0295456U (en) | 1989-01-18 | 1989-01-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP354089U JPH0295456U (en) | 1989-01-18 | 1989-01-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0295456U true JPH0295456U (en) | 1990-07-30 |
Family
ID=31205264
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP354089U Pending JPH0295456U (en) | 1989-01-18 | 1989-01-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0295456U (en) |
-
1989
- 1989-01-18 JP JP354089U patent/JPH0295456U/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0295456U (en) | ||
| JPH048153U (en) | ||
| JPH03107736U (en) | ||
| JPH0466625U (en) | ||
| JPS6446862U (en) | ||
| JPH0341349U (en) | ||
| JPH01106949U (en) | ||
| JPS635527U (en) | ||
| JPH0363251U (en) | ||
| JPH0426500U (en) | ||
| JPS6013064U (en) | mirror device | |
| JPS63118659U (en) | ||
| JPS6339757U (en) | ||
| JPS6368054U (en) | ||
| JPH0365338U (en) | ||
| JPS63106227U (en) | ||
| JPS63159440U (en) | ||
| JPS60108159U (en) | motor | |
| JPS63168554U (en) | ||
| JPH02143603U (en) | ||
| JPH0330149U (en) | ||
| JPS59195220U (en) | pin joint mechanism | |
| JPS6392971U (en) | ||
| JPS59105834U (en) | Connection structure of auxiliary paddy receiver in the paddy receiver of combine harvester | |
| JPH048154U (en) |