JPH0426500U - - Google Patents

Description

[Brief explanation of the drawing]

Fig. 1 is a configuration diagram showing a dual port memory according to an embodiment of this invention, Fig. 2 is a timing diagram according to an embodiment of this invention when only write access occurs, and Fig. 3 is a read access. 4 is a timing diagram according to an embodiment of this invention when only a read access occurs, and FIG. 4 shows a timing diagram according to an embodiment of this invention when a write access to an address different from this address occurs immediately after a read access occurs. Figure 5 shows the light
A timing diagram according to an embodiment of this invention when a read access to an address different from this address occurs immediately after an access occurs.・A timing diagram according to an embodiment of this invention when an access occurs; FIG. 7 is a timing diagram according to an embodiment of the invention when a read access to the same address as this address occurs immediately after a write access occurs. Timing diagram FIG. 8 is a block diagram showing a conventional dual port memory. In the figure, 1 is the first address, 2 is the second address, 3 is the control signal, 4 is the memory flag,
5 is a flag control signal, 6 is a memory controller, 7 is a first memory, 8 is a second memory, 9 is a first memory control signal, 10 is a second memory control signal, 11 is a first address , first data, 12
are the second address, second data, 13 is the first data, and 14 is the second data. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Scope of utility model registration request] A read port that accepts read access only, a write port that accepts write only, and a memory controller that generates control signals so that even if accesses from the read port and write port occur simultaneously, they can be processed at the same time. Dual port memory featuring: