JPH0362788A - Reference signal generating circuit device - Google Patents

Abstract

PURPOSE:To form a reference signal generating circuit device with a few components and simple circuit constitution by resetting a reference signal of the same period as that of a vertical synchronizing signal and sending the reference signal again based on a signal sent from a count section and a waveform shaping circuit. CONSTITUTION:For example, 4 vertical synchronizing signals or over are missing, a counter 7 changes an output signal level into an H level from an L level so far when the count reaches 4 or over. Then since a signal of an H level is fed to one input of an AND circuit 3, a 1st vertical synchronizing signal after the missing is fed to a waveform shaping circuit 2. When a pulse signal a3 is sent from the waveform shaping circuit 2, the AND circuit 3 sends a signal of an H level to a pulse generating circuit 4. Then the pulse generating circuit 4 resets a reference signal sent in self-running and sends a reference signal of the same period as that of the vertical synchronizing signal again newly synchronously with the pulse signal a3.

Description

[Detailed Description of the Invention] [9 Industrial Applications] The present invention is directed to a video tape recorder (hereinafter referred to as VTR).
The present invention relates to a reference signal generating circuit device used in a Zaho circuit.

"Conventional technology/problems" Conventionally, the reference signal used in the servo circuit of a VTR is 1. During playback (J is the system clock), and during recording (J vertical synchronization signal are separated and used.

Since the vertical synchronization signal is used during recording in this way, in areas with weak electric fields where the S/N ratio is low, the vertical synchronization signal may be missing or noise may be mixed in, making it impossible to obtain an appropriate reference signal. There are cases.

As a device for eliminating such drawbacks, for example, as disclosed in Japanese Patent Application Laid-Open No. 62-294384, a superimposed synchronization signal detection circuit detects vertical synchronization in order to prevent malfunctions due to lack of vertical synchronization signals. It detects that the signal is not continuously supplied, changes the preset value to the preset counter of the preset circuit, and sets the count width of the precent counter to the same value as the period of the vertical synchronization signal to create a reference signal. I have to.

However, the reference signal generating circuit disclosed in the above-mentioned publication has a problem in that its circuit configuration is complicated and the number of parts is large.

The present invention has been made to solve these problems, and an object of the present invention is to provide a reference signal generating circuit device with a simple circuit configuration and a small number of parts.

[Means for Solving the Problems] The present invention provides a waveform shaping circuit that creates a pulse signal synchronized with an externally supplied vertical synchronization signal, and a two-leg waveform shaping circuit that controls the supply of the vertical synchronization signal to the bipedal waveform shaping circuit. A switch, a pulse generation circuit that sends out a pulse signal with the same period as the vertical synchronization signal as a reference signal, and a pulse generation circuit that counts the number of pulses of the signal sent out by the pulse generation circuit described in 1. a count section that sends out a control signal, and a reference signal that is sent out from the pulse generation circuit based on the synchronization pulse signal sent out by the waveform shaping circuit and the control signal sent out by the count section, into the synchronization pulse signal (1). a first reset signal generating section that sends out a synchronous reset signal; and a count value counted by the two-legged counting section and sent out from the counting section based on the synchronizing pulse signal and the reference signal. and a second reset signal generation section that resets the control signal.

[Operation] With this configuration, during reproduction, the switch is turned off, no vertical synchronizing signal is supplied to the waveform shaping circuit, and the pulse generating circuit sends out a free-running reference signal.

During recording, the switch is turned on, and the pulse generation circuit resets the free-running reference signal with the reset signal sent from the first reset signal generator, and generates a new reference signal at the same period as the vertical synchronization signal. Start sending out.

[Embodiment] The circuit device shown in FIG. 1, which is an embodiment of the reference signal generating circuit device of the present invention, is used in a servo circuit of a VTR.

In FIG. 1, on the input side of a switch l that is turned on and off by a control signal sent from a system control section (not shown), a vertical A synchronizing signal is supplied, and the output side of the switch 1 is connected to a waveform shaping circuit 2 that forms the waveform of the synchronizing signal. The output side of the waveform shaping circuit 2 is
Connected to the input sides of AND circuit 3 and AND circuit 5, A
The output side of the ND circuit 3 is connected to a pulse generation circuit 4.

When the pulse generating circuit 4 is not supplied with any signal, it runs at the same frequency as the synchronizing signal that is separated from the signal sent out by the video circuit section, but when the pulse generating circuit 4 is supplied with the pulse signal from the AND circuit 3, This is a circuit that generates a pulse signal with the same period as the synchronization signal and a very narrow pulse width by re-triggering the two-legged self-running signal. Further, the signal sent out from the pulse generating circuit 4 becomes a reference signal in the servo circuit of the VTR.

The output side of the pulse generation circuit 4 is connected to a servo circuit (not shown), and also to the other input terminal of an AND circuit 5, and is connected to a counter 7 that counts the number of pulses of the reference signal sent out by the pulse generation circuit 4. Connected to the input side.

Further, the output side of the AND circuit 5 is connected to the reset terminal of the counter 7 via a delay circuit 6.

Therefore, the AND circuit 5 sends out a signal at T (level) to the delay circuit 6 only when both the waveform shaping circuit 2 and the pulse generation circuit 4 send out signals at the high (H) level, and the delay circuit 6 sends out a signal at the T (level). is delayed and sent as a reset signal to the counter 7. When the reset signal is supplied, the counter 7 resets the counted value. still,
Counter 7 (J1 counts up the number of pulses of the supplied reference signal from 0, and when the count reaches 4 or more, continues to send out an H level signal until the next reset signal is supplied:'), other than that The count number is low (L)
Sends a level signal. Furthermore, until the first reset signal is supplied, a signal at level I is sent out.

Further, the output side of the counter 7 is connected to the input side of the AND circuit 3. Therefore, the AND circuit 3 sends an output signal to the pulse generation circuit 4 only when an H level signal is supplied from the waveform shaping circuit 2 and the counter 7.

The operation of the reference signal generation circuit device of this embodiment configured as described above will be described below with reference to FIGS. 1 and 2.

First, the operation during playback will be explained.

The switch 1 is set to the OFF state by a control signal sent from the system control section. Therefore, since the vertical synchronization signal is not supplied to the pulse generation circuit 4 via the waveform shaping circuit 2 and the AND circuit 3, the pulse generation circuit 4 uses a free-running signal with the same period as the vertical synchronization signal as a reference signal. It is sent to a servo circuit (not shown). In this case,
No signal is sent from the waveform shaping circuit 2; AN
Since the D circuit 5 sends out an L level signal, the counter 7
The count number is not reset (reset) and becomes 4 or more, which is the set value. Therefore, the counter 7 receives the H level signal as A.
Continue sending to ND circuit 3 (J.However, waveform shaping circuit 2
Since it does not send out a signal, the output signal of the AND circuit 3 is always at the I7 level, and the pulse generating circuit 4 is never reset. Therefore, the pulse generation circuit 4 sends a pulse signal having the same period as the vertical synchronization signal during recording to the servo circuit as a reference signal.

Next, during recording, the switch l is turned on by the control signal sent from the system control circuit, and depending on the form of the vertical synchronization signal supplied, the following three
There are several possible states, and the operation in each will be explained below.

First, as shown in the range ■ in Figure 2, if a vertical synchronizing signal is supplied to The first pulse signal aO sent out is supplied to the AND circuit 3. Note that the counter 7 sends out an H level signal until the first reset signal is supplied.
Since the AND circuit 3 is supplied with the H level signal, the AND circuit 3 sends the H level signal to the pulse generating circuit 4 when the pulse signal aO is supplied.

Therefore, in the pulse generation circuit 4, the free-running reference signal is reset by this pulse signal supplied from the AND circuit 3, and thereafter, a new vertical synchronization signal as shown in FIG. 2B is generated at the same period. A pulse signal is created and sent out as a reference signal.

In addition, the waveform shaping circuit 2 supplies an H level signal, and the pulse generating circuit 4 sends out a reference signal, so that the second
As shown in FIG. The signal d0 is sent to the counter 7 as a reset signal.

As shown in FIG. 2E, when the counter 7 is supplied with this pulse signal dO, it stops sending out the H level signal that it has been sending out so far. Therefore, since the AND circuit 3 is supplied with an L level signal from the counter 7, the AND circuit 3 is supplied with an L level signal from the counter 7.
Circuit 3 sends out an I7 level signal, and pulse generation circuit 4
The pulse signal having the same period as the vertical synchronizing signal generated in the vertical synchronizing signal is not set, and the pulse signal serving as the reference signal continues to be sent out at the same period as the vertical synchronizing signal as shown in FIG. 2B. Therefore, the pulse signal that is the reference signal is supplied to the counter 7, but as mentioned above, the AND circuit 5 sends out an H level signal at a constant cycle, so the counter 7 is reset at a constant cycle from the delay circuit 6. When the signal is supplied, the count number of the counter 7 is reset at a fixed period, and the count value of the counter does not exceed 1. Therefore, the counter 7 always sends out a signal at L level, and from then on, the count value of the counter 7 is reset at a constant period. operates in the same manner.Therefore, the pulse generating circuit 4 sends out a reference signal having the same period as the vertical synchronizing signal.

Next, as shown in the range H in Figure 2, when the pulse generation circuit 4 is sending out two consecutive reference signals, the vertical synchronization signal supplied to the waveform shaping circuit 2 is missing. In this case, for example, as shown in FIG. 2, when the vertical synchronizing signal a1 that should originally be supplied is missing, an L level signal is sent from the waveform shaping circuit 2 to the AND circuit 3. However, since the L level signal is supplied from the counter 7 to the two consecutive AND circuits 3, even if a pulse supplied from the waveform shaping circuit 2 is missing, the pulse will not be sent from the AND circuit 3. There is no change in the signal level
The pulse generation circuit 4 remains at the same level, and the pulse generation circuit 4 is not reset, but sends out a reference signal having the same period as the vertical synchronization signal as in the above case.

What is different from the case in the above I range is that the signal level sent by the waveform shaping circuit 2, which is originally at the H level, becomes the I7 level, so the signal level sent by the AND circuit 5 remains at the L level. . Therefore, the counter 7 signal is not supplied from the delay circuit 6, and the counter I value of the counter 7 becomes 1. However, if the current setting value of the counter 7 is 4, the count value is smaller than 4. In particular, the output signal of the upstream counter 7 remains at the L level, and the pulse generating circuit 4 continues to send out the reference signal with the same period as the vertical synchronizing signal without missing the signal as shown in FIG. 2B. Ru.

Next, as shown in the range ■ in Fig. 2, several vertical synchronization signals supplied to the waveform shaping circuit 2 are missing consecutively when the above-mentioned reference signal is being sent from the pulse generation circuit 4. In this case, as described above, if the number of missing pieces is 3 or less, which is smaller than the set value of 4 set in the counter 7, the same operation as in the case of two consecutive single missing pieces is performed.

On the other hand, if four or more vertical synchronization signals are missing, the AND circuit 5 continues to send out the I7 level signal as described above (so the delay circuit 6 supplies an H level reset signal to the counter 7 First, counter 7 has a count of 4.
At this point, the output signal level is changed from the previous L level to the I4 level. Therefore, AND circuit 3
Since an I-■ level signal will be supplied to one input terminal, the first vertical synchronization signal after the loss is supplied to the waveform shaping circuit 2 through the switch 1, and from the waveform shaping circuit 2 to the flow shown in FIG. At the time when the pulse signal a3 shown in is sent out, AN
The D circuit 3 sends a 14-level signal to the pulse generation circuit 4. By being supplied with this I4 level signal, the pulse generating circuit 4 resets the reference signal that has been sent out in a self-running manner until now by resetting the pulse signal a3 as shown in FIG. 2B.
In synchronization with , a new reference signal having the same period as the vertical synchronization signal is started to be sent again. Also, since the waveform shaping circuit 2 starts sending out the signal of 1 (), the AND circuit 5 again sends out the signal of 1 (1), so the count value of the counter 7 is reset, and the output signal level of the counter 7 becomes L5 again
Return to level. The subsequent operations are similar to those described in 1-1.

Next, as shown in the range ■ in FIG. 2, when the pulse generating circuit 4 is sending out the above-described reference signal j knee, the vertical synchronizing signal supplied to the waveform shaping circuit 2 is A
If a noise such as shown in 1 or 2 is mixed in, in this case, the same operation as in the range of H described above will be performed, and the pulse generating circuit 4 will not be reset by the noise an. The reference signal is sent out at the same period as before.

Next, when recording only the audio signal and not the video signal, the mode is switched from the 0) control circuit (not shown), and the pulse generation circuit 4 operates in the same manner as during playback. A reference signal can be created more easily.1 As described above, according to the reference signal creation channel device of this embodiment,
If the vertical synchronization signal is lost 91 times under a weak electric field,
If the -r channel of the television program being recorded is changed, or if the recording signal is disturbed and the vertical synchronization signal is continuously lost or disturbed, only the audio signal is recorded. If there is no vertical synchronization signal, two noises are mixed in the duplex synchronization signal - bow, and if no, etc. ωf4
1 (articles (4-F-' iKore-(, positive,
It is possible to create a standard reference signal.

Incidentally, such a reference signal generation circuit device is equipped with a circuit for detecting a drop in the vertical synchronization signal, such as the Hanawa semi-signal generation circuit disclosed in the ``Nippon Publication,'' and the signal sent from this circuit is a 1-point preset value. without performing any action such as changing the AND
By detecting the loss of the vertical synchronization signal in the circuit and resetting the free-running reference signal with the same cycle as the vertical synchronization signal, we provide a reference signal generation circuit device with a small number of parts that make up the circuit. can do.

[Effects of the Invention] As described in detail above, according to the present invention, the reference signal having the same period as the vertical synchronization signal is reset based on the signals sent out by the counting unit and the waveform shaping circuit, and the reference signal By transmitting the signal as a reference signal, it is possible to provide a reference signal generating circuit device with a simple circuit configuration and a small number of parts.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the reference signal generation circuit device of the present invention. FIG. 2 is a time chart showing the operation of the reference signal generation circuit device shown in FIG. 1. Waveform shaping circuit , pulse generation circuit, counter.

Claims (1)

[Claims] (1) A waveform shaping circuit that creates a pulse signal synchronized with an externally supplied vertical synchronization signal, and a switch that controls the supply of the vertical synchronization signal to the waveform shaping circuit, with the same period as the vertical synchronization signal. a pulse generation circuit that sends out a pulse signal as a reference signal, a counting section that counts the number of pulses of the reference signal sent out by the pulse generation circuit and sends out a control signal in accordance with the count value, and a waveform shaping circuit that a first reset signal generation section that sends out a signal that resets the reference signal sent out from the pulse generation circuit in synchronization with the synchronization pulse signal based on the synchronization pulse signal sent out and the control signal sent out by the counting section; , a second reset signal generating section that resets the count value counted by the counting section and the control signal sent from the counting section based on the synchronization pulse signal and the reference signal. A reference signal generating circuit device characterized by: