JPS61274479A - Video signal processor - Google Patents
Video signal processorInfo
- Publication number
- JPS61274479A JPS61274479A JP60116217A JP11621785A JPS61274479A JP S61274479 A JPS61274479 A JP S61274479A JP 60116217 A JP60116217 A JP 60116217A JP 11621785 A JP11621785 A JP 11621785A JP S61274479 A JPS61274479 A JP S61274479A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- timing
- video signal
- horizontal
- video
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims description 6
- 230000001360 synchronised effect Effects 0.000 abstract description 5
- 150000001875 compounds Chemical class 0.000 abstract 2
- 230000001172 regenerating effect Effects 0.000 abstract 1
- 230000008929 regeneration Effects 0.000 abstract 1
- 238000011069 regeneration method Methods 0.000 abstract 1
- 239000002131 composite material Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/91—Television signal processing therefor
- H04N5/93—Regeneration of the television signal or of selected parts thereof
- H04N5/932—Regeneration of analogue synchronisation signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/06—Generation of synchronising signals
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/12—Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising
- H04N5/126—Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising whereby the synchronisation signal indirectly commands a frequency generator
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/91—Television signal processing therefor
- H04N5/92—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Television Signal Processing For Recording (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明はビデオ信号処理装置に関し、特にビデオ信号中
の同期信号に関連するタイミング信号群を用いてビデオ
信号の処理を行う装置に関する。DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to a video signal processing device, and more particularly to a device that processes a video signal using a timing signal group related to a synchronization signal in the video signal.
く開示の概要〉
本明細書及び図面は、ビデオ信号中の同期信号に関連す
るタイミング信号群を用いてビデオ信号の処理を行う装
置に於いて、水平同期信号の周波数に関連する周波数の
高周波信号をカウントして水平走査同期に係る第1のタ
イミング信号群を形成すると共に、該第1のタイミング
信号群中の1つをカウントして垂直走査周期に係る第2
のタイミング信号群を形成し、またビデオ信号の不連続
時水平同期信号を用い前記第1のタイミング信号群を計
数する計数手段をリセットする様に構成することにより
、常に水平同期信号とタイミングの一致したタイミング
信号群を得ることができる様になり、これに伴って常に
良好なビデオ信号処理を行うことのできるビデオ信号処
理装置を提供する技術について開示を行うものである。Summary of the Disclosure> The present specification and drawings describe a device that processes a video signal using a timing signal group related to a synchronization signal in a video signal, which uses a high-frequency signal having a frequency related to the frequency of a horizontal synchronization signal. is counted to form a first timing signal group related to horizontal scanning synchronization, and one of the first timing signal groups is counted to form a second timing signal group related to vertical scanning period.
By forming a timing signal group and resetting the counting means for counting the first timing signal group using the horizontal synchronization signal when the video signal is discontinuous, the timing always matches the horizontal synchronization signal. The present invention discloses a technique for providing a video signal processing device that can obtain a group of timing signals and thereby consistently perform good video signal processing.
〈従来の技術〉
一般にビデオテープレコーダやビデオカメラ等に於いて
はビデオ信号の処理を行うため、同期信号に係るタイミ
ングのタイミング信号群を発生する発生器(以下単にS
SGと称す)を設け、このSSGの出力を用いてクラン
プ、自動利得制御、カラーエンコード等の信号処理が行
われてきた。<Prior art> Generally, in video tape recorders, video cameras, etc., in order to process video signals, a generator (hereinafter simply referred to as S) that generates a group of timing signals related to a synchronization signal is used.
The output of this SSG has been used to perform signal processing such as clamping, automatic gain control, and color encoding.
従来SSGに於いて出力するタイミング信号群をビデオ
信号と同期させるためには以下の如き方法がとられてい
た。即ち、まず所謂自動周波数制御回路(AFC)によ
りビデオ信号中の水平同期信号(HD)に関連した周波
数の高周波クロックを得、このクロックをカウントする
と共にこの計数値をビデオ信号中の垂直同期信号でリセ
ットすることによって各タイミング信号を得ていた。Conventionally, the following method has been used to synchronize a group of timing signals output in an SSG with a video signal. That is, first, a high-frequency clock having a frequency related to the horizontal synchronizing signal (HD) in the video signal is obtained by a so-called automatic frequency control circuit (AFC), this clock is counted, and this counted value is used as the vertical synchronizing signal in the video signal. Each timing signal was obtained by resetting.
〈発明が解決しようとする問題点〉
ところが何らかの原因でビデオ信号に不連続が発生した
場合その直後に於いてタイミング信号群とビデオ信号中
の同期信号との間には整合がとれていない、従来の装置
に於いては不連続発生後の最初に入力されるVDにより
カウンタがリセットされるが、これまでの間はビデオ信
号の処理は全く行えなかった。またビデオ信号中のHD
とのタイミングの整合はAFCにて徐々に行われるが。<Problems to be Solved by the Invention> However, when discontinuity occurs in the video signal for some reason, there is no consistency between the timing signal group and the synchronization signal in the video signal immediately after the discontinuity occurs. In this device, the counter is reset by the first VD input after the occurrence of discontinuity, but until then no video signal processing could be performed. Also, HD in the video signal
Timing alignment with the AFC is gradually performed.
この整合に必要な期間がどうしても長くかかってしまい
、この期間良好なビデオ信号の処理が行えないという問
題があった。There is a problem in that the period necessary for this matching is unavoidably long, and good video signal processing cannot be performed during this period.
本発明は上述の如き問題に鑑みてなされたものであって
、常に良好なビデオ信号処理を行うことができるビデオ
信号処理装置を提供することを目的とする。The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a video signal processing device that can always perform good video signal processing.
く問題点を解決するための手段〉
上述の如き目的下に於いて、本発明に於いてはビデオ信
号中の水平同期信号を用い、その周波数に関連する周波
数の高周波信号を発生する手段と、該高周波信号をカウ
ントして水平走査周期に係る第1のタイミング信号群を
形成する第1の計数手段と、該第1のタイミング信号群
中の1つをカウントして垂直走査周期に係る第2のタイ
ミング信号群を形成する第2の計数手段と、前記ビデオ
信号の不連続時前記水平同期信号を用い、前記第1の計
数手段をリセットする手段とを設け、前記第1及び第2
のタイミング信号群を用いて前記ビデオ信号の処理を行
う様に構成している。Means for Solving the Problems> With the above object in mind, the present invention provides means for generating a high frequency signal of a frequency related to the horizontal synchronizing signal in a video signal, using the horizontal synchronizing signal in the video signal; a first counting means that counts the high frequency signals to form a first timing signal group related to the horizontal scanning period; and a second counting means that counts one of the first timing signal groups and forms a second timing signal group related to the vertical scanning period. and means for resetting the first counting means using the horizontal synchronization signal when the video signal is discontinuous,
The video signal is processed using a group of timing signals.
く作 用〉
上述の如く構成することによって、ビデオ信号に不連続
が発生した直後に於いても、第1のタイミング信号群は
水平同期信号のタイミングと整合することになり、これ
に伴って常に良好なる信号処理の行うことができるビデ
オ信号処理装置が得られる様になった。By configuring as described above, the first timing signal group will match the timing of the horizontal synchronization signal even immediately after a discontinuity occurs in the video signal, and accordingly, the first timing signal group will always match the timing of the horizontal synchronization signal. It has become possible to obtain a video signal processing device that can perform excellent signal processing.
〈実施例〉
以下、本発明を円状トラックに1フイ一ルド分のビデオ
信号を記録し、これを繰り返し連続して再生することに
より静止画を得るシステム(スチルビデオシステムと界
す)に適用した場合の実施例を用いて詳細に説明する。<Embodiment> Hereinafter, the present invention will be applied to a system (hereinafter referred to as a still video system) that records a video signal for one field on a circular track and obtains a still image by repeatedly and continuously reproducing the video signal. This will be explained in detail using an example in which the case is as follows.
第1図は本発明の一実施例としてのスチルビデオシステ
ムの構成を示す図である0図中端子1より入力された同
期信号を含むビデオ信号は、記録信号処理回路2にて記
録に適した信号形態とされ、スイッチ3のR側端子を介
してヘッド4により磁気シート上の円状トラックにその
1フイ一ルド分が記録される。一方、再生時に於いては
ヘッド4によりピックアップされたビデオ信号は再生信
号処理回路6にて元に信号形態に戻され、更に出力処理
回路7でNTSC信号等のテレビジョン信号の形態とさ
れ、後述する様に複合デコーダ21より得た同期信号を
付加して端子8より出力する。FIG. 1 is a diagram showing the configuration of a still video system as an embodiment of the present invention. In FIG. One field is recorded in the form of a signal by the head 4 via the R side terminal of the switch 3 on a circular track on the magnetic sheet. On the other hand, during playback, the video signal picked up by the head 4 is returned to its original signal form by the playback signal processing circuit 6, and further converted into the form of a television signal such as an NTSC signal by the output processing circuit 7, which will be described later. A synchronizing signal obtained from the composite decoder 21 is added thereto and output from the terminal 8 as shown in FIG.
スイッチ9は記録時にはR側、再生時にはP側に接続さ
れ、記録時に於いては記録信号処理回路2に入力される
ビデオ信号を、再生時に於いては再生信号処理回路6よ
り出力されるビデオ信号を出力することになる。スイッ
チ9の出力ビデオ信号は複合同期信号分離回路10を介
して水平同期信号分離回路11及び垂直同期信号分離回
路18に供給される。The switch 9 is connected to the R side during recording and to the P side during playback, and connects the video signal input to the recording signal processing circuit 2 during recording, and the video signal output from the playback signal processing circuit 6 during playback. will be output. The output video signal of the switch 9 is supplied to a horizontal synchronizing signal separating circuit 11 and a vertical synchronizing signal separating circuit 18 via a composite synchronizing signal separating circuit 10.
回路11で分離されたHDは周知の位相制御ループ回路
(PLL)13に供給され、HDに位相同期した高周波
クロック信号、例えば260fnCfoは水平走査周波
数)のクロックが形成される。この高周波クロックはカ
ウンタ14でカウントされ、その計数値が2111.0
(nは整数)になる毎に自動的にリセットされる。The HD separated by the circuit 11 is supplied to a well-known phase control loop circuit (PLL) 13, and a high frequency clock signal whose phase is synchronized with the HD, for example, a clock of 260fnCfo (horizontal scanning frequency) is generated. This high frequency clock is counted by the counter 14, and the counted value is 2111.0.
(n is an integer) is automatically reset.
カウンタ14に出力を用いて水平デコーダ15はHDに
タイミングの一致したタイミング信号群を発生する。こ
のタイミング信号としては例えばクランプパルス形成用
、AGC用のキードパルス形成用のタイミング信号等が
ある。また複合デコーダ21にもカウンタ14の計数デ
ータ等が供給され、カウンタ16にはHDに関連する周
波数の計数パルスを供給する。更に水平デコーダ15は
後に、出力処理回路7で付加されるHDと同じタイミン
グのfHの周波数信号をPLI、13にフィードバック
しAFCを形成している。Using the output from the counter 14, the horizontal decoder 15 generates a timing signal group whose timing coincides with the HD. This timing signal includes, for example, a timing signal for forming a clamp pulse and a keyed pulse for AGC. The composite decoder 21 is also supplied with the count data of the counter 14, and the counter 16 is supplied with count pulses at frequencies related to HD. Furthermore, the horizontal decoder 15 later feeds back the fH frequency signal at the same timing as the HD added by the output processing circuit 7 to the PLI, 13 to form an AFC.
カウンタ16は水平デコーダ15より発生される計数パ
ルスを1フイ一ルド分計数すれば自動的にリセットする
。これに伴い垂直デコーダ17はVDに係るタイミング
のタイミング信号を発生する。このタイミング信号とし
ては7レーム構成のビデオ信号に於ける第1フイールド
と第2フイールドの切換信号等がある。垂直デコーダ1
7は更にカウンタ16の計数データ等を複合デコーダ2
1に供給する。The counter 16 is automatically reset when counting pulses generated by the horizontal decoder 15 for one field. Accordingly, the vertical decoder 17 generates a timing signal with timing related to VD. This timing signal includes a switching signal between the first field and the second field in a video signal having a 7-frame configuration. Vertical decoder 1
7 further sends the count data of the counter 16 to a composite decoder 2.
Supply to 1.
複合デコーダ21はこれらのデータに応じてHD、VD
にタイミングの合ったタイミング信号を発生する0例え
ばこのタイミング信号としては出力処理回路7に於いて
再生ビデオ信号に付加される複合同期信号等がある。The composite decoder 21 decodes HD and VD according to these data.
For example, this timing signal includes a composite synchronization signal that is added to the reproduced video signal in the output processing circuit 7.
ビデオ信号に不連続が発生する要因としては、記録再生
の切換によるもの、ヘッド4により再生する円状トラッ
クの切換によるものがあるが、これら記録再生の切換、
再生トラックの切換等はシステムコントローラ12によ
り制御されている。Discontinuities can occur in video signals due to switching of recording and reproduction, and switching of circular tracks reproduced by the head 4.
Switching of reproduction tracks and the like are controlled by a system controller 12.
これに伴いシステムコントローラ12はビデオ信号に不
連続が発生した直後、リセットゲート19を1水平走査
期間、リセット端子)20を1垂直走査期間開く、従っ
てカウンタ14のリセット端子にはビデオ信号が不連続
になった直後のI(Dに応じたリセットパルスが1つ、
カウンタ16のリセット端子にはビデオ信号が不連続に
なった直後のVDに応じたリセットパルスが1つ夫々供
給される。Accordingly, immediately after the discontinuity occurs in the video signal, the system controller 12 opens the reset gate 19 for one horizontal scanning period and the reset terminal 20 for one vertical scanning period, so that the discontinuous video signal appears at the reset terminal of the counter 14. Immediately after the I (D), there is one reset pulse,
One reset pulse corresponding to VD immediately after the video signal becomes discontinuous is supplied to each reset terminal of the counter 16.
従ってビデオ信号が不連続となった直後に於いても、水
平デコーダ15、垂直デコーダ17及び複合デコーダ2
1より出力されるタイミング信号群のタイミングはHD
に正確に一致される。これによって記録信号処理回路2
、再生信号処理回路6及び出力処理回路7による信号処
理は常に良好に行われることになる。Therefore, even immediately after the video signal becomes discontinuous, the horizontal decoder 15, vertical decoder 17, and composite decoder 2
The timing of the timing signal group output from 1 is HD.
is matched exactly. As a result, the recording signal processing circuit 2
, the signal processing by the reproduced signal processing circuit 6 and the output processing circuit 7 is always performed satisfactorily.
〈発明の効果〉
以上説明した様に本発明によれば常に良好な信号処理を
行うことのできるビデオ信号処理回路を得るものである
。<Effects of the Invention> As explained above, according to the present invention, it is possible to obtain a video signal processing circuit that can always perform good signal processing.
第1図は本発明の一実施例としてのスチルビデオシステ
ムの構成を示す図である。
2は記録信号処理回路、6は再生信号処理回路、7は出
力信号処理回路、11は水平同期信号分離回路、12は
システムコントローラ、13はPLL、14はカウンタ
、15は水平デコーダ、16はカウンタ、17は垂直デ
コーダ、18は垂直同期信号分離回路、19.20は夫
々リセットゲート、21は複合デコーダである。FIG. 1 is a diagram showing the configuration of a still video system as an embodiment of the present invention. 2 is a recording signal processing circuit, 6 is a reproduction signal processing circuit, 7 is an output signal processing circuit, 11 is a horizontal synchronizing signal separation circuit, 12 is a system controller, 13 is a PLL, 14 is a counter, 15 is a horizontal decoder, and 16 is a counter. , 17 is a vertical decoder, 18 is a vertical synchronizing signal separation circuit, 19 and 20 are reset gates, and 21 is a composite decoder.
Claims (1)
する周波数の高周波信号を発生する手段と、該高周波信
号をカウントして水平走査周期に係る第1のタイミング
信号群を形成する第1の計数手段と、該第1のタイミン
グ信号群中の1つをカウントして垂直走査周期に係る第
2のタイミング信号群を形成する第2の計数手段と、前
記ビデオ信号の不連続時前記水平同期信号を用い、前記
第1の計数手段をリセットする手段とを具え、前記第1
及び第2のタイミング信号群を用いて前記ビデオ信号の
処理を行うビデオ信号処理装置。Means for generating a high frequency signal of a frequency related to the horizontal synchronization signal in the video signal, and a first counter for counting the high frequency signal to form a first timing signal group related to the horizontal scanning period. means, second counting means for counting one of the first timing signals to form a second timing signal group related to a vertical scanning period; and when the video signal is discontinuous, the horizontal synchronizing signal and means for resetting the first counting means,
and a video signal processing device that processes the video signal using a second timing signal group.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60116217A JPS61274479A (en) | 1985-05-29 | 1985-05-29 | Video signal processor |
US06/840,942 US4729024A (en) | 1985-03-19 | 1986-03-18 | Synchronizing pulse signal generation device |
US07/098,022 US4851910A (en) | 1985-03-19 | 1987-09-17 | Synchronizing pulse signal generation device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60116217A JPS61274479A (en) | 1985-05-29 | 1985-05-29 | Video signal processor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61274479A true JPS61274479A (en) | 1986-12-04 |
Family
ID=14681730
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60116217A Pending JPS61274479A (en) | 1985-03-19 | 1985-05-29 | Video signal processor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61274479A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6455982A (en) * | 1987-08-27 | 1989-03-02 | Sony Corp | Video reproducing device |
JPH066758A (en) * | 1992-02-11 | 1994-01-14 | Internatl Business Mach Corp <Ibm> | Signal processor for correcting distortion of display image |
-
1985
- 1985-05-29 JP JP60116217A patent/JPS61274479A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6455982A (en) * | 1987-08-27 | 1989-03-02 | Sony Corp | Video reproducing device |
JPH066758A (en) * | 1992-02-11 | 1994-01-14 | Internatl Business Mach Corp <Ibm> | Signal processor for correcting distortion of display image |
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