JP2604914B2 - Motor speed control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motor speed control device used in the fields of OA equipment, audiovisual equipment, and the like.

[0002]

2. Description of the Related Art In recent years, as OA equipment and audiovisual equipment have become more sophisticated and more sophisticated, the motors used in these equipment have often required advanced speed control. I have.

For example, there is a strong demand for a motor that starts instantaneously and rotates stably at a predetermined speed with high accuracy.

In the motor speed control technology, a speed control based on a phase, that is, a PLL control system, has been conventionally devised as a system in which the most accurate control characteristics can be expected.

A conventional motor speed control device employing the PLL control system will be described below.

FIG. 4 shows a circuit configuration of a conventional motor speed control device. In FIG. 4, 1 is a motor, and 2 is a reference clock generator for generating a reference clock CLo. Reference numeral 3 denotes a speed detector which outputs a speed signal FGo having a frequency corresponding to the speed of the motor 1. The output signal CLo of the reference clock generator 2 and the output signal FGo of the speed detector 3 are phase comparators. 4 as input signals CL and FG. The output of the phase comparator 4 is input to the error amplifier 5, and the error
Is input to the power amplifier 6. The power amplifier 6
Are connected to the motor 1.

The operation of the conventional motor speed control device configured as described above will be described below.
First, consider the case where the speed of the motor 1 is low and the frequency of the output signal CLo of the reference clock generator 2 is higher than the frequency of the output signal FGo of the speed detector 3. At this time, CL
o and FGo are input as the respective input signals CL and FG of the phase comparator 4. The phase comparator 4 has a frequency difference between the respective input signals, and the frequency of the input signal CL is higher than the frequency of the input signal FG. If the signal is high, the operation is performed so as to output a low-level signal to the output signal PD. When the output signal PD of the phase comparator 4 becomes Low level, the error amplifier 5 and the power amplifier 6 operate to increase the power supply to the motor 1 and accelerate the motor 1. That is, when the speed of the motor 1 is lower than the speed corresponding to the reference clock signal CLo, the motor 1 is accelerated.

Next, consider the case where the speed of the motor 1 is high and the frequency of the output signal CLo of the reference clock generator 2 is lower than the frequency of the output signal FGo of the speed detector 3. At this time, CLo and FGo are input as the input signals CL and FG of the phase comparator 4, however, the phase comparator 4 has a frequency difference between the input signals and the frequency of the input signal CL is equal to the input signal FG. When the frequency is lower than the frequency, the operation is performed so as to output a High level signal to the output signal PD. When the output signal PD of the phase comparator 4 becomes High level, the error amplifier 5 and the power amplifier 6 operate to reduce the amount of power supplied to the motor 1 and decelerate the motor 1. That is, the motor 1 outputs the reference clock signal C
If the speed is higher than the speed corresponding to Lo, the motor 1 will be decelerated.

Next, the speed of the motor 1 becomes a speed corresponding to the reference clock signal CLo, and the reference clock generator 2
Is the output signal F of the speed detector 3
Consider the case where the frequency matches the frequency of Go. At this time, CL
o and FGo are input as the respective input signals CL and FG of the phase comparator 4. When the frequencies of the respective input signals match, the phase comparator 4 outputs to the output signal PD the phase difference between the respective input signals. It operates to output a signal having a corresponding duty, that is, a phase error signal. When the phase comparator 4 outputs a phase error signal having a duty corresponding to the phase difference between the input signals CL and FG as the output signal PD, the error amplifier 5 and the power amplifier 6 respond accordingly.
Operates to control the speed of the motor 1 by adjusting the amount of power supply to the motor 1. That is, the motor 1 is driven at a speed corresponding to the reference clock signal CLo.

As described above, when the speed of the motor is different from the speed corresponding to the reference clock signal, the motor is accelerated or decelerated so as to have the speed corresponding to the reference clock signal. The driving power is controlled in accordance with the phase error signal between the reference clock signal and the speed signal, and operates so as to maintain a constant speed.

Here, the operation of the phase comparator 4 will be described in some detail. The phase comparator 4 receives the input signal C
If there is a frequency difference between L and FG and the frequency of the input signal CL is higher than the frequency of the input signal FG, the output signal PD
, A low-level signal is output to the output signal PD when the frequency of the input signal CL is lower than the frequency of the input signal FG.
When the frequencies of the input signals match, a signal having a duty corresponding to the phase difference between the input signals, that is, a phase error signal is output to the output signal PD. As described above, it operates to output. Here, a method of determining the frequency difference between the input signals CL and FG will be described.

FIG. 5 is an operation waveform diagram of the phase comparator 4.
In FIG. 5, P _CL, P _FG is a pulse signal generated at the time of the fall of the input signal _CL, FG, P CL, P
_FG has the same frequency and the same phase as CL and FG, respectively. P _CL and P _FG are generated inside the phase comparator 4, and the phase comparator 4 determines the frequency difference between CL and FG based on P _CL and P _FG . In other words, P as compared to the P _FG
High _CL pulse incidence of, P _CL to the pulse generation interval of P _FG
Is continued twice or more, it is determined that the frequency of CL is higher than the frequency of FG, and a low level is output to the output signal PD (period a in FIG. 5). In this state, it increased pulse incidence of P _FG, to determine the pulse of the pulse generation interval P _FG of P _CL is generated twice, and the moment, and the frequency of the FG of CL match, A signal having a duty corresponding to the phase difference between CL and FG is output to the output signal PD (period b in FIG. 5). In this state, further increased pulse incidence of P _FG, when the pulse of the pulse generation interval P _FG of P _CL occurs more than once, the frequency of CL is determined to lower than the frequency of the FG, the output signal The High level is output to the PD (period c in FIG. 5). In this state, in turn decreases the pulse generation rate of P _FG, the pulses P _CL is generated twice the pulse generation interval of P _FG, and that moment, the match again the frequency of the frequency and FG of CL The signal having the duty according to the phase difference between CL and FG is output to the output signal PD (d period in FIG. 5).

As described above, the phase comparator 4 determines the frequency difference between the input signals CL and FG, and the operation is as shown in FIG. Note that the signal LD in FIGS. 4 and 5 is a signal that goes to a low level when the frequencies of CL and FG match, and whether the CL and FG are in phase synchronization (in a state where the frequencies match) or not. This is a phase synchronization detection signal for detecting whether or not the state is a deviation state (a state where the frequencies do not match). That is, when the LD is at the low level, it means that the LD is in a phase-locked state, and Hi
When it is at the gh level, it means that the phase is out of phase.

[0014]

As described above, in the conventional configuration, the phase comparator determines that the frequency of each of the input signals CL and FG coincides with each other, and that the frequency of CL is equal to the frequency of FG. in higher than discriminates the moment the pulse P _FG pulse generation interval of P _CL occurs twice, in a lower than the frequency of the frequency FG of CL, P to the pulse generation interval of P _{FG The} operation is performed so as to determine at the moment when the _CL pulse is generated twice.

[0015] However, at the moment of the determination, when the pulse of the pulse and P _FG of P _CL occur simultaneously, the phase comparator malfunctions can not confirm the operation, so that each input signal CL, the FG It is impossible to determine that the frequencies match and the phase is synchronized, and it becomes difficult to control the motor speed (PLL control) according to the phase difference signal between the reference clock signal CLo and the speed signal FGo. Had a point.

The present invention solves the above-mentioned conventional problems, and it is possible to reliably determine that the frequencies of the input signals CL and FG of the phase comparator coincide with each other, and that a phase-synchronized state is attained. An object of the present invention is to provide a motor speed control device capable of controlling the speed of a motor by PLL control.

[0017]

In order to achieve the above object, a motor speed control apparatus according to the present invention comprises a motor, a speed detector for outputting a signal having a frequency corresponding to the speed of the motor, and a motor. A reference clock generator that outputs a reference clock signal serving as a speed reference, a phase comparator that compares phases of output signals of the speed detector and the reference clock generator, and outputs a phase error signal; An error amplifier for amplifying a phase error signal output of a detector, a power amplifier for amplifying an output of the error amplifier to supply power to the motor, an output signal of the speed detector and an output signal of the reference clock generator Comprises simultaneous input preventing means that operates to prevent simultaneous input to the phase comparator, and canceling means that operates to cancel the operation of the simultaneous input preventing means. The simultaneous input prevention means operates when the output signal of the speed detector and an output signal of the reference clock generator is a phase deviation state, the releasing means,
The output signal of the speed detector and the output signal of the reference clock generator are configured to operate after a predetermined time has elapsed after the phase synchronization state.

[0018]

With this configuration, the output signal of the speed detector and the output signal of the reference clock generator are prevented from being simultaneously input to the phase comparator, and therefore, the malfunction of the phase comparator is prevented. As a result, it is reliably determined that the output signal of the speed detector and the output signal of the reference clock generator are in a phase-synchronous state, and the motor speed can be quickly and stably controlled by the PLL control.

[0019]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a circuit configuration of a motor speed control device according to the present invention. 1, parts having the same functions as those of the circuit configuration of the conventional motor speed control device shown in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted.

In FIG. 1, reference numeral 10 denotes a simultaneous input preventing means, which includes an oscillator 11 and inverting gate circuits 12, 14, 16 to.
21 and flip-flop circuits 13 and 15. That is, the output of the oscillator 11 is input to the inverting gate circuit 12, and one output of the inverting gate circuit 12 is input to the CL input of the flip-flop circuit 13,
The other output is input to the CL input of the flip-flop circuit 15 by turning the inverting gate circuit 14. The input of the inverting gate circuit 16 has an output signal CLo of the reference clock generator 2.
And one output of the inverting gate circuit 16 is input to the D input of the flip-flop circuit 15. The other output of the inverting gate circuit 16 and the Q output of the flip-flop circuit 15 are connected to the inverting gate circuit 1 respectively.
7 and 18 are commonly connected and input as an input signal CL of the phase comparator 4. An output signal FGo of the speed detector 3 is input to an input of the inverting gate circuit 19, and one output of the inverting gate circuit 19 is input to a D input of the flip-flop circuit 13. The inverting gate circuit 19
And the Q output of the flip-flop circuit 13 are commonly connected via inverting gate circuits 20 and 21, respectively, and input as an input signal FG of the phase comparator 4. Reference numeral 30 denotes a releasing means, which is constituted by a delay circuit 31 and inverting gate circuits 32-35. That is, the phase synchronization detection signal LD of the phase comparator 4 is input to the input of the delay circuit 31, and the output is input to the inverting gate circuit 32. One output of the inverting gate circuit 32 is input to the inverting gate circuit 34 via the inverting gate circuit 33, and the other output is input to the inverting gate circuit 35. One output of the inverting gate circuit 34 is input to the input of the inverting gate circuit 17, and the other output is input to the input of the inverting gate circuit 20. One output of the inversion gate circuit 35 is input to the input of the inversion gate circuit 18, and the other output is input to the input of the inversion gate circuit 21.

Here, each inverting gate circuit and each flip-flop circuit are integrated with IIL logic.
Injection Logic, and these outputs are open collector outputs. The input has been subjected to a pull-up process.

Except for the above, the circuit configuration is the same as that of the conventional motor speed control device shown in FIG. 4, and a description thereof will be omitted.

The operation of the motor speed control device configured as described above will be described below.

In FIG. 1, similarly to the conventional motor speed control device shown in FIG. 4, when the speed of the motor 1 is different from the speed corresponding to the reference clock signal CLo, the speed of the motor 1 is increased to the speed corresponding to the reference clock signal. Alternatively, when the speed is reduced to a speed corresponding to the reference clock signal CLo, the driving power is controlled in accordance with the phase error signal between the reference clock signal CLo and the speed signal FGo, and the device operates to maintain a constant speed. However, the simultaneous input preventing means 10 and
The provision of the release means 30 is significantly different from the conventional motor speed control device.

Simultaneous input prevention means 10 and cancellation means 30
The operation of will be described below. First, the operation of the simultaneous input preventing means 10 will be described with reference to FIGS. FIG.
From the state in which the frequency of the reference clock signal CLo, which is the output signal of the reference clock generator 2, is higher than the frequency of the speed signal FGo, which is the output signal of the speed detector 3,
This shows the moment when the frequency o increases, the frequency of the reference clock signal CLo matches the frequency of the speed signal FGo, and the phase is synchronized. As shown in FIG. 2, the reference clock signal CLo is applied to the inverted gate rotations 12, 14, 1
6, 18 and the flip-flop circuit 15, the oscillator 1
The signal is input to the phase comparator 4 as a signal CL synchronized with the falling timing of one output clock signal C. on the other hand,
The speed signal FGo is converted into a signal F synchronized with the rising timing of the output clock signal C of the oscillator 11 by the inverting gate circuits 12, 19, and 21 and the flip-flop circuit 13.
G is input to the phase comparator 4. That is, the input signals CL and FG of the phase comparator 4 are synchronized with the falling and rising timings of the output clock signal C of the oscillator 11, respectively.
Is input at a timing shifted by at least a half clock of the clock signal C. Therefore, the phase comparator 4 shown in the conventional example
The pulse signals P _CL and P _FG generated inside are not generated at the same time, and the phase synchronization state can be reliably determined. Note that, in the above operation, a release unit 3 described later is used.
The output of the inverting gate circuit 34, which is the output of 0, is Low, and the output of the inverting gate circuit 35 has a high impedance.

As described above, the simultaneous input preventing means 10 operates to reliably determine the phase synchronization state. However, after the phase synchronization state is established, this operation is necessary to perform stable PLL speed control. And signals CL and FG generated at the same timing as the actual reference clock signal CLo and speed signal FGo, instead of the signals CL and FG synchronized with the clock signal C, must be input to the phase comparator 4.

The means for realizing this is the releasing means 30 described below. The operation of the release means 30 will be described below with reference to FIGS. FIG. 3 shows an operation after the phase comparator 4 determines the phase synchronization state and sets the phase synchronization detection signal LD to Low. 1 and 3, when the LD goes low, the delay circuit 31 sets the LD low.
and outputs a signal DLD from become ow is the time elapsed after the Low indicated by t _d. When the output signal DLD of the delay circuit 31 becomes Low, the output of the inverting gate circuit 34 becomes High.
Impedance, and the output of the inverting gate circuit 35 becomes L
ow. That is, the reference clock signal CLo and the speed signal FGo are directly input to the respective inputs CL and FG of the phase comparator 4 via the inverting gate circuits 16 and 17 and the inverting gate circuits 19 and 20. The operation of the prevention means 10 is released. After the operation of the simultaneous input preventing means 10 is released, signals CL and FG generated at the same timing as the reference clock signal CLo and the speed signal FGo are input to the phase comparator 4, and the stable P
Speed control by LL control becomes possible.

As described above, according to this embodiment, the simultaneous input preventing means 10 is provided, and the reference clock signal CLo output from the reference clock generator 2 and the speed signal FGo output from the speed detector 3 are compared in phase. By preventing simultaneous input to the comparator 4, malfunction of the phase comparator 4 can be prevented beforehand, and the phase synchronization state can be reliably determined. Further, a canceling means 30 is provided to cancel the operation of the simultaneous input preventing means 10 after the phase synchronization state, and the reference clock signal CL output from the reference clock generator 2 is released.
o and the speed signal FGo output from the speed detector 3 are directly input to the phase comparator 4 to provide a stable PLL.
Speed control by control is possible.

The output signal DLD of the delay circuit 31, which is a component of the canceling means 30, is a signal indicating that the operation of the simultaneous input preventing means 10 has been canceled and the speed control by the stable PLL control is being performed. It is also possible to use as.

[0031]

As described above, according to the present invention, a simultaneous input preventing means which operates so as to prevent the output signal of the speed detector and the output signal of the reference clock generator from being simultaneously input to the phase comparator, Releasing means for releasing the operation of the simultaneous input preventing means, wherein the simultaneous input preventing means is provided when the output signal of the speed detector and the output signal of the reference clock generator are in a phase deviation state. Operating, the release means operates after a predetermined time has elapsed after the output signal of the speed detector and the output signal of the reference clock generator have entered a phase-locked state, thereby ensuring a reliable phase. It is possible to realize an excellent motor speed control device that can determine the synchronization state and quickly perform speed control by stable PLL control.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a motor speed control device according to an embodiment of the present invention.

FIG. 2 is an operation explanatory diagram in FIG.

FIG. 3 is an explanatory diagram of the operation in FIG. 1;

FIG. 4 is a circuit configuration diagram of a motor speed control device in a conventional example.

FIG. 5 is an explanatory diagram of the operation in FIG. 4;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Motor 2 Reference clock generator 3 Speed detector 4 Phase comparator 5 Error amplifier 6 Power amplifier 10 Simultaneous input prevention means 30 Release means

Continuing on the front page (72) Inventor Hiromitsu Nakano 1006 Kazuma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (72) Inventor Masao Mizumoto 2-18 Keihanhondori Moriguchi City Sanyo Electric Co., Ltd. (72 Inventor Koichiro Ogino 2-18 Keihanhondori, Moriguchi City Sanyo Electric Co., Ltd. (72) Inventor Tsutomu Shimazaki 2-18 Keihanhondori Moriguchi City Sanyo Electric Co., Ltd. (56) References JP 60 JP-A-125184 (JP, A) JP-A-63-54613 (JP, A) JP-A-63-198586 (JP, A) JP-A-63-287381 (JP, A)

Claims (1)

(57) [Claims] 1. A motor, a speed detector for outputting a signal having a frequency corresponding to the speed of the motor, a reference clock generator for outputting a reference clock signal serving as a speed reference of the motor, and the speed detector A phase comparator for comparing a phase of an output signal from the reference clock generator with the reference clock generator to output a phase error signal; an error amplifier for amplifying a phase error signal output from the phase comparator; A power amplifier that supplies power to the motor; and a simultaneous input prevention circuit that operates to prevent an output signal of the speed detector and an output signal of the reference clock generator from being input to the phase comparator at the same time. Means, and cancellation means operable to cancel the operation of the simultaneous input prevention means,
The simultaneous input preventing means operates when the output signal of the speed detector and the output signal of the reference clock generator are out of phase synchronization, and the canceling means operates with the output signal of the speed detector and the reference signal. A motor speed control device configured to operate after a predetermined time elapses after an output signal of a clock generator is in a phase synchronization state.