JPH05135438A - Servo circuit - Google Patents

Abstract

PURPOSE:To stabilize and shorten the pull-in time of a phase system servo after moving to a high speed reproducing mode without preparing previously much data and without using complicated circuit constitution. CONSTITUTION:A control signal is 1/(2N+1) frequency divided by a frequency divider 5 having a counter 5a counting the control signal recoded on a tape at the time of the high speed reproduction of (2N+1) times speed, and a phase of a phase reference signal having a slope and having a falling edge from 'H' level to 'L' level at the position of 1/2 period from the center of the slope and a phase of a frequency dividing control signal is compared by a phase comparator circuit 4, and relevant compared result is outputted as a phase error signal for controlling the phase of a motor and simultaneously the counter value of the counter 5a is preset to N synchronizing with the falling edge of the phase reference signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capstan servo circuit of a magnetic recording / reproducing apparatus using a tape such as a VTR.

[0002]

2. Description of the Related Art A VTR has a high speed reproduction mode for reproducing at a tape speed different from that at the time of recording. And, even in such a high-speed playback mode, tape running is stabilized,
Speed control and phase control are performed so that the phase relationship with the rotary head becomes a specific relationship.

Conventionally, as a VTR for executing such control, Japanese Patent Application Laid-Open No. 1-16198 (H02P5 / 0).
In 0), at the time of shifting from the normal reproduction mode to the high-speed reproduction (picture search) mode, a frequency divider for dividing the phase comparison signal recorded on the tape, that is, the control signal (CTL) is used as a reference of the phase system. By resetting at an appropriate timing according to the speed of playback that is faster than the signal,
A method has been proposed for stabilizing and shortening the phase pull-in after the velocity system is stabilized.

For example, FIG. 4 is a circuit block diagram of this prior art. In FIG. 4, 1 is a speed detection circuit for inputting an FG signal of a capstan motor and outputting a speed error signal, and 2 is a speed error signal. PWM for PWM conversion
The conversion circuit 3 is a speed system lock detection circuit that receives a PWM-converted speed error signal as an input and checks whether the speed of the capstan motor is within a predetermined range (depending on the mode).

Reference numeral 4 is a phase comparison circuit, 5 is a reproduction control signal (CTL) frequency dividing circuit, 6 is a reference signal generating circuit, and 7 is a reference signal generating circuit.
Is a mono-multi for tracking, 8 is a mono-multi that delays the tracking mono-multi output, 9 is a phase error signal that is maintained at 50% during operation, and the phase error signal that is the phase comparison output when not in operation The phase error signal fixing circuit 10 that outputs to the PWM conversion circuit 10 is a PWM conversion circuit that performs PWM conversion of the phase error signal.

Reference numeral 11 is a D-type flip-flop for detecting the delayed mono-multi 8 output immediately after the speed of the capstan motor is within a predetermined range, and 12 is a reset pulse generation for detecting the rise of the output of the D-type flip-flop 11. Circuit.

Metastable period (TD) of delay monomulti 8
Is set as TD = TS-TC / 2. Here, TS is the time from the output of the tracking monomulti 7 to the slope center of the trapezoidal wave h, and TC is the reproduction control signal period during high-speed reproduction.

Next, the operation will be described with reference to FIG. When the signal a instructing the high speed reproduction becomes H level, the reference of the speed of the capstan motor is changed and the capstan motor is accelerated. Then, as shown in b, the output of the speed system lock detection circuit 3 becomes the L level indicating that the speed is not within the predetermined range. And during this mode change,
The phase error fixing circuit 9 operates and the phase error signal becomes PW.
It is fixed so that the duty of M is 50%. This control is performed by the output of the D-type flip-flop 11. When the speed of the capstan motor is within the predetermined range, the output of the speed system lock detection circuit 3 becomes H level, the output of the delayed mono-multi 8 immediately after that becomes the H level, and at the trailing edge of the output of the delayed mono-multi 8 immediately after that. , This H level is latched. Therefore, the output of the D-type flip-flop 11 becomes H level, and the fixation of the phase error signal is released. Further, the frequency divider 5 (the frequency division ratio is set for high-speed reproduction) 5 is reset at the rising timing of the output of the D-type flip-flop 11, and the frequency division operation of the reproduction control signal is substantially started. ..

Therefore, the rising phase of the output of the frequency divider 5 appears within ± TC / 2 from the center of the slope of the trapezoidal wave h, and the variation of the pull-in time can be suppressed.

[0010]

According to the above-mentioned prior art, the appearance range of the frequency-divided CTL signal closest to the phase lock position is calculated in advance, and the frequency divider is generated by the timing signal created by mono-multi based on this data. Therefore, a large number of circuits are required, and the metastable time TD of the delay monomulti is required to be stored in advance in accordance with the speed number.

[0011]

SUMMARY OF THE INVENTION The present invention provides a speed control system for controlling the speed of a tape feed motor so that the FG signal of the tape feed motor has a predetermined cycle, and a control signal recorded on the tape. Has a counter to count,
A frequency divider that outputs a frequency division control signal when the count value of the counter reaches 2N + 1 during high-speed reproduction of (2N + 1) times, and has a slope and is 1 from the center of the slope.
The phase of the phase reference signal having a falling edge from the H level to the L level at the position of / 2 cycle and the phase of the frequency division control signal are compared, and the comparison result is used as a phase error signal for phase control of the motor. A phase comparison means for outputting is provided, and the count value of the counter is preset to N in synchronization with the falling edge of the phase reference signal in a speed servo unlocked state in which the rotation speed of the motor is out of a predetermined range. To do.

[0012]

According to the present invention, the frequency division control signal can be generated by the control signal existing in the slope period among the (2N + 1) frequency division control signals when the phase control is started after the mode transition to the high speed reproduction mode. it can.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of this embodiment, and FIG.
The same parts as those in FIG. The difference from FIG. 4 is that the D-type flip-flop 11, the delay monomulti 8, and the reset pulse creation circuit 12 are removed, and preset data is created in accordance with the frequency division ratio setting data for setting the double speed number. The data creating circuit 20, the gate circuit 21 for controlling the input of the preset data created by this creating circuit to the frequency dividing circuit 5, and the preset timing of the frequency divider 5 are detected to create a HIGH / LOW switching timing signal. That is, the switching timing signal detection circuit 22 to be supplied to the gate circuit 21 is added.

Next, the operation of this embodiment will be described. Immediately after the shift to the high speed reproduction mode, the speed servo lock detection circuit 3 shifts to the L level, and the phase error fixing circuit is fixed so that the phase error signal of the capstan phase system is fixed at 50% during the period when the L level is maintained. 9 becomes operational. In this state, the capstan motor is accelerated by the capstan speed servo, and when the speed reaches a predetermined speed, the speed servo lock detection circuit 3 detects this and the output of the detection circuit 3 shifts to the H level. The phase error
The fixed circuit 9 stops fixing the error signal to 50% and starts the phase system control. That is, the phase comparison output of the phase comparison circuit 4 is input to the PWM conversion circuit 10 without any processing.

On the other hand, the reference signal c emitted from the reference signal generating circuit 6 is delayed by the tracking monomulti 7, and a trapezoidal wave having a phase slope in the phase comparison circuit 4 based on the output d of the monomulti 7. In addition to creating h, an H / L switching timing signal is created by the creating circuit 22 like k in synchronization with the falling edge of the trapezoidal wave and applied to the gate circuit 21.

The gate circuit 21 is temporarily opened when a switching timing signal is input, and the frequency division ratio setting data "(2N + 1)" (which is set in the decoder 5b forming the frequency divider 5 together with the counter 5a ( Data "N" excluding the least significant bit (N: integer) is set in the counter 5a as preset data as indicated by m in FIG. This set operation is executed only until the above-mentioned speed system servo lock is detected by the detection circuit 3, that is, while the detection circuit output maintains the L level. That is, the gate circuit 21 presets the counter 5a only when the H / L switching timing signal is input while the output of the speed system servo lock detection circuit 3 continues to be at the L level, and the output of the detection circuit 3 is at the H level. Between H /
Even if the L switching timing signal is input, the preset is not performed. The decoder 5b receives the division ratio setting data and the count value of the counter 5a that counts the CTL of i, issues a division CTL when the count value matches the division ratio setting data indicated by j, and outputs this output. Counter 5
a is reset.

By the way, the phase system of the capstan is a trapezoidal wave having a phase system slope created from a reference signal,
The error output data of the phase system is obtained by sampling with the CTL signal. The center of the slope of this trapezoidal wave is set to the phase where the CTL should be locked, and outside this slope, it is set to the H level or the L level as shown in FIG. Where this H or L
Level durations are generally set to be equal. That is, H / L is switched at a phase ½ frame away from the center of the slope. Also, the tape speed for high-speed playback is (2
N + 1) times, and the CTL at this time is 1 / (2N +
It is divided into 1) and used for phase control.

From the above, when there is a divided CTL at the center of the slope during high speed reproduction of (2N + 1) times speed, as shown in FIG. 3, the Nth CTL and N + 1 from this CTL.
There will be a trapezoidal wave switching portion from H to L in the middle of the th CTL.

Therefore, as described above in the explanation of the operation of FIG. 1, immediately before the start of the phase control in the high speed reproduction mode, the count value of the counter 5a is changed at the level switching portion of the phase trapezoidal wave from H to L. If is preset to “N”, the frequency division CTL can be created with the CTL closest to the center of the slope, and the frequency division CTL can be quickly pulled into the trapezoidal wave slope after the phase control is started.

In this way, the slope is sampled at the rising edge of the frequency division CTL drawn into the slope of the trapezoidal wave, and this sampling data is output as phase error data to the PWM conversion circuit 10 to become PWM. The phase is controlled by being supplied to the motor driver.

[0022]

As described above, according to the present invention, (2N +
1) It is possible to create a frequency division control signal from the control signals that exist in the slope period among the frequency division control signals that exist, without preparing for a metastable period for each speed of mono-multi and without having a complicated circuit. It is possible to stabilize and shorten the pull-in time of the phase system servo after shifting to the high speed reproduction mode.

[Brief description of drawings]

FIG. 1 is a circuit block diagram of an embodiment of the present invention.

FIG. 2 is a timing chart of an example of the present invention.

FIG. 3 is a diagram showing a relationship between a phase trapezoidal wave and a control signal.

FIG. 4 is a circuit block diagram of a conventional example.

FIG. 5 is a timing chart of a conventional example.

[Explanation of symbols]

 3 speed system servo lock detection circuit 5a counter 5 frequency divider 4 phase comparison circuit 22 H / L switching timing signal 20 preset data creation circuit

Claims (1)

[Claims] 1. A speed control system for controlling the speed of the tape feed motor so that the cycle of the FG signal of the tape feed motor becomes a predetermined cycle, and a counter for counting the control signals recorded on the tape. 2N + 1) A frequency divider that outputs a frequency division control signal when the count value of the counter reaches 2N + 1 during high-speed reproduction at a high speed, and a slope that has a slope and a half cycle from the center of the slope. Phase comparison means for comparing the phase of the phase reference signal having a falling edge to the level with the frequency division control signal and outputting the comparison result as a phase error signal for phase control of the motor, When the speed of the motor is out of the predetermined range and the speed servo is unlocked, the counter count is synchronized with the falling edge of the phase reference signal. The servo circuit is characterized by presetting the threshold value to N.