JPH0360291A - ディジタルｖｔｒ - Google Patents

ディジタルｖｔｒ

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Publication number
JPH0360291A
JPH0360291A JP1194115A JP19411589A JPH0360291A JP H0360291 A JPH0360291 A JP H0360291A JP 1194115 A JP1194115 A JP 1194115A JP 19411589 A JP19411589 A JP 19411589A JP H0360291 A JPH0360291 A JP H0360291A
Authority
JP
Japan
Prior art keywords
circuit
pulse
signal
clock
pll
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1194115A
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English (en)
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JP3028819B2 (ja
Inventor
Masuo Umemoto
梅本　益雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
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Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP01194115A priority Critical patent/JP3028819B2/ja
Publication of JPH0360291A publication Critical patent/JPH0360291A/ja
Application granted granted Critical
Publication of JP3028819B2 publication Critical patent/JP3028819B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05171—Chromium [Cr] as principal constituent
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05563—Only on parts of the surface of the internal layer
    • H01L2224/05564—Only on the bonding interface of the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/11472—Profile of the lift-off mask
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13006—Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Television Signal Processing For Recording (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はディジタルＶＴＲにおけるクロック抽出回路、
とくに位相同期（Ｐｈａｓｅ　Ｌｏｃｋ　Ｌｏｏｐ以下
、ＰＬＬと略す。）回路に関する。
〔従来の技術〕
従来からＰＬＬ回路をディジタルＶＴＲのクロック抽出
回路に用いる事は多くの提案があり、例えば特公昭６２
−４７３７５に示されている。
〔発明が解決しようとする課題〕
上記した例の如き従来技術は、ＰＬＬ回路のディジタル
ＶＴＲへの適用に関する種々の１１！題（例えば、記録
時と異なる速度で再生するときのＰＬＬの構成、応答性
の敗善など）に対する対策を提供している。しかし、デ
ィジタルＶＴＲでは磁気テープと磁気ヘッドが接触した
状態で使用することが前提とされるため１例えば、磁気
テープにキズがつく、磁気ヘッドにゴミが付くなどの事
故が発生し、再生信号のＳ／Ｎが極端に低下し、再生デ
ータからクロック成分が抽出できない状態が発生するこ
とがある。
従来のＰＬＬ回路においてはこれらの対処について充分
な検討がなされておらず、ディジタルＶ’ｒＲ全体のシ
ステムとしての使い勝手が低いという問題点があった。
本発明の目的はこのように、ＰＬＬのクロックと再生デ
ータがアンロック状態になった事を検出アラーム信号を
発生させ、装置の停止などの処置を取らせるなどの処理
を取らせ、ＶＴＲシステムの信頼性を向上させる工つの
手段を提供することである。
〔課題を解決するための手段〕
上記目的を達成するために、本発明においては磁気テー
プから得られた再生データはテープヘッド系の周波数特
性を補償され、その後、２値信号とされる。さらにこの
信号の立上り、立下りで所定のパルス幅を持つパルスを
発生させ、ＰＬＬ回路で発生させたクロックを上記パル
スでラッチする。ラッチ出力はディジタルＶＴＲの全体
システムの要求に従って加工され、アラーム情報等に利
用される。
〔作用〕
ＰＬＬＩＥ回路で発生させたクロックは本来再生データ
に同期するように作製されているので、再生データで発
生させた所定パルスで、クロックをラッチすると、正常
（ロック）状態では、ラッチ出力はハイレベルを保つ、
一方、アンロック状態ではランダムにハイレベル、ロー
レベルが現われる。
よって、このラッチ出力を用いれば、容易にＰＬＬ出力
クロックと再生データ間のロック状態を検出することが
できる。
上記手段２作用の説明から５本発明は記録に用いた変調
コードと無関係にＰＬＬのロック、アンロック状態が検
出できる。
〔実施例〕
以下、本発明の一実施例を図によって説明する。
第１図は実施例における信号系統図であり、第２図は第
１図の各部の波形を示す。
磁気テープ１に記録されていた信号は磁気ヘッド２によ
って再生され、再生等化回路３でテープヘッド系の周波
数特性が補正され、２値の信号Ａとなる。信号Ａの立上
り、立下りにおいて、再生データのパルス間隔の半分に
相当するパルス幅を有するパルスＢがパルス発生口路４
で発生させられる。ＰＬＬ回路１１は位相検出回路５．
ローパスフィルタ６、電圧制御発振回路７で構成される
。
パルスＢは位相検出回路５に人力され、電圧制御発振回
路７のクロック出力Ｃとの間の位相が検出される。位相
検出回路５の出力である位相誤差信号はローパスフィル
タ６を介して電圧制御発振回路７に入力され、再生デー
タパルスＢとクロックＣが同期するようにフィードバッ
クループが形成される。
信号Ｂの立下りでクロック出力Ｃをラッチ回路８でラッ
チすると、ラッチ出力りは第２図のように信号Ｂとクロ
ックＣが同期している場合、ハイレベルとなる。
信号ＢとクロックＣが同期していない場合はＤ′のよう
な信号となり、ハイレベルとローレベルがランダムに現
われる。
ローパスフィルタ９を通せば、信号りあるいはＤ′のレ
ベルがそれぞれおよそＶおよび−Ｖ（ただしＶは信号り
のパルス高）として得られるので、比較回路１０の一方
の入力に一■の電圧を与えておけば。
比較回路１０の出力はＰＬＬＩＥＪ路が再生データに同
期しているかどうかを示すことになる。
その他の実施例としては、第３図に示すように信号りを
ディジタルＶＴＲ全体をコントロールするシステム系１
２に送り、ラッチ回路１２−１で間欠的に信号りをシス
テムに取り込む。間欠周期としてはたとえばテレビジョ
ンのフィールド周期（約１５　ｍ５ｅｃ）とすることが
適当である。
取り込んだ信号りが連続ｎ回（ｎは１０回程度で良い）
ローレベルであれば、Ｐ　Ｌ　Ｌ　回路がアンロック状
態であると判断できる。勿論ハイレベルが現われている
時はロック状態を表示する命令とする。
なお、Ｖ　ＴＲを記録時と異なるテープ速度で再生する
、いわゆるシャトル再生やスロー再生を行なう場合があ
る。この場合、記録トラックを横切るように再生ヘッド
が移動するので、再生信号はとぎれとぎれになる。この
ため、ノーマル再生以外ではＰＬＬ回路のアンロックは
ＰＬＬ回路以外の原因で発生する。従ってノーマル再生
以外ではＰＬＬ回路のアンロックを表示しない事にする
。
また、ノーマル再生時でしかも連続ｎ回信号りがローレ
ベルになった時にアンロック表示の命令を出すようにす
ることもできる。
なお、ノーマル再生時の中に同期再生（記録しながら再
生する場合）の状態も含めることができる。
〔発明の効果〕
本発明によれば、ノーマル再生時や同時再生時において
、ＰＬＬが正常に動作しているかどうかの情報を容易に
検出でき、それを表示させるシステムが実現できる。こ
のため、異常が発生した場合の故障場所をすばやく限定
することが可能となり、信頼性の高いＶＴＲの操作が可
能となる。
【図面の簡単な説明】
第１図は本発明の一実施例の検出回路の回路ブロック図
、第２図は第１図における各部の信号波形図、第３図は
別の実施例のシステムフロー図である。 ３・・・再生等化回路、８・・・ラッチ回路、１工・・
・ＰＬＬ回路。 ■ ＞ｒ 豹 図 図

Claims (1)

  1. 【特許請求の範囲】 １、再生データに同期したクロックを発生するＰＬＬ回
    路と、ＰＬＬ回路の出力クロックを再生データでラット
    するラッチ回路を設けたことを特徴とするＰＬＬ回路の
    ロック、アンロック検出回路。 ２、上記検出回路の出力信号をノーマル再生時だけ使用
    することを特徴とするＶＴＲシステムコントロール系。
JP01194115A 1989-07-28 1989-07-28 Ｐｌｌ回路のロツク，アンロツク検出回路 Expired - Lifetime JP3028819B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP01194115A JP3028819B2 (ja) 1989-07-28 1989-07-28 Ｐｌｌ回路のロツク，アンロツク検出回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP01194115A JP3028819B2 (ja) 1989-07-28 1989-07-28 Ｐｌｌ回路のロツク，アンロツク検出回路

Publications (2)

Publication Number Publication Date
JPH0360291A true JPH0360291A (ja) 1991-03-15
JP3028819B2 JP3028819B2 (ja) 2000-04-04

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05211910A (ja) * 1992-02-10 1993-08-24 Yoshida Kogyo Kk <Ykk> シートクッション用の面ファスナー止具
JPH05211909A (ja) * 1992-02-10 1993-08-24 Yoshida Kogyo Kk <Ykk> シートクッション用の面ファスナー片連結体
US5342569A (en) * 1992-03-23 1994-08-30 Yoshida Kogyo K.K. Method of attaching a fastening tape to a molded article

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05211910A (ja) * 1992-02-10 1993-08-24 Yoshida Kogyo Kk <Ykk> シートクッション用の面ファスナー止具
JPH05211909A (ja) * 1992-02-10 1993-08-24 Yoshida Kogyo Kk <Ykk> シートクッション用の面ファスナー片連結体
US5342569A (en) * 1992-03-23 1994-08-30 Yoshida Kogyo K.K. Method of attaching a fastening tape to a molded article

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JP3028819B2 (ja) 2000-04-04

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