JPH0360179B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a field effect transistor in which an active layer of a gate region and source and drain ion implantation regions are disposed on the main surface of a semiconductor substrate. It is.

[Conventional technology]

For example, a Schottky junction gate field effect transistor (hereinafter referred to as "field effect transistor") using a compound semiconductor such as GaAs
MESFET) is widely used as an individual semiconductor element that constitutes high-frequency amplifiers and oscillators.
Recently, they are also playing an important role as basic elements of high-frequency and high-speed integrated circuits. By the way, the high frequency figure of merit of such MESFET is
As is well known, transfer conductance gm
It is expressed as gm/C _g using the gate capacitance C _g .

That is, the high frequency figure of merit is improved by increasing gm and decreasing C _g . In this case, g.m.
Focusing on
It is known that gm=gm ₀ /(1+gm ₀ Rs) is expressed by gm ₀ and the series added resistance Rs between the source and gate. In other words, due to Rs, the effective gm becomes smaller than the intrinsic gm ₀ .
Therefore, the question is how to reduce this Rs.
This is one key to obtaining large transfer conductance and improving the high frequency characteristics of MESFET.

A self-alignment method between the gate-shot junction and the source and drain regions is known as a method for reducing Rs. There are several concrete methods for this, but the typical one is shown in FIG. That is, selective ions of, for example, Si as an n-type impurity are implanted into the main surface of a high-resistance compound semiconductor substrate 11 such as GaAs to form a primary ion-implanted layer 12 that will become an active layer (FIG. 4a). A silicon nitride film 13 having a thickness of 0.15 μm is deposited on the main surface, for example, by plasma CVD.
Furthermore, a three-layer resist having a three-layer structure including, for example, a resist 14 ₁ , an insulating film 14 ₂ such as SiO ₂ , and a resist 14 ₃ is formed on this. Next, the uppermost resist 14 ₃ of the three-layer resist 14 is patterned by a light exposure method, and using this as a mask, the lower insulating film 14 ₂ is patterned, and then the lowermost resist 14 3 is patterned.
4 ₁ is sequentially processed by reactive ion etching (RIE) or the like to make openings in the source/drain formation regions and selectively expose the silicon nitride film 13.
Next, using this three-layer resist 14 as a mask,
For example, Si is selectively ion-implanted as a type impurity to form a high-density ion-implanted layer 15 having an impurity density approximately 10 times that of the primary ion-implanted layer 12 (FIG. 4b). An insulating film, for example a 0.3 μm thick SiO ₂ film, is deposited on the main surface of the substrate thus formed. Subsequently, the above deposited on the three-layer resist 14
Lift and lift the SiO ₂ film together with the three-layer resist 14.
By removing the SiO 2 film 16 by turning it off, the SiO ₂ film 16 having a pattern that is an inversion of the pattern of the bottom resist 14 ₁ of the three-layer resist is replaced with the silicon nitride film 1
3 (Fig. 4c). By this lift-off processing, the SiO ₂ film 16 is formed almost directly above the high-density ion implantation layer 15. In this case, the bottom layer resist 14 ₁ of the three-layer resist is side-etched with respect to the middle layer 14 ₂ , that is, the fourth
If you make it into a T-shape as shown in Figure b, the above
The SiO ₂ film 16 covers the high-density ion-implanted layer 15 by an amount corresponding to the side etching above the implanted end of the high-density ion-implanted layer 15 . Next, in order to activate the ion-implanted layer, heat treatment is performed at 800° C. for 20 minutes in a nitrogen atmosphere, for example.

Next, silicon nitride film 13 and SiO ₂ film 16
A resist pattern having openings only in the portions corresponding to the source and drain electrodes is formed on the main surface of the substrate on which the
The SiO ₂ film 16 and the silicon nitride film 13 are removed by, for example, reactive ion etching and plasma etching, respectively. Next, using the resist pattern, for example, AuGe/Ni is deposited as an ohmic metal, lifted off, and the remaining portion is alloyed to form the source electrode 1.
7. Form the drain electrode 18. Next, a resist pattern is formed on the main surface of the substrate with an opening only in the portion corresponding to the gate electrode metal, and etching is performed using an etching method that has a higher etching rate for the silicon nitride film than the SiO ₂ film, such as plasma etching or etching. The silicon nitride film 13 is etched using reactive ion etching to expose the surface of the primary ion implantation layer 12. Next, after depositing a metal forming a shot junction with GaAs, unnecessary portions are lifted off together with the resist to form a gate electrode 19 (FIG. 4d).

[Problem that the invention seeks to solve]

However, the self-aligned MESFET obtained by this manufacturing method has a drawback in that the gate electrode 19 rises above the insulating film 16. That is, according to this structure, the capacitance C _g between the _gate electrode and the channel layer is, as shown in FIG. With the addition of stray capacitance Cp, C _g
=C _j +2Cp. As the value of C _g increases, the high-frequency and high-speed characteristics of the element deteriorate, as described above.
This will reduce the performance of the GaAs IC.

[Means for solving problems]

In order to solve these problems, the present invention eliminates the part of the gate electrode that rises above the insulating film. After depositing the gate electrode material itself on the surface so that the surface is flat, the gate electrode material is etched using an anisotropic etching method in which the etching rate is high in the direction perpendicular to the direction parallel to the main surface. In the second method, a film is further deposited on the gate electrode material to make the surface flat, and then the film is etched by the above-mentioned anisotropic etching, and then the gate electrode material is etched using the remaining film as a mask. A third method is to deposit a gate electrode material, then tilt the main surface with respect to the direction of incidence of etching particles, and perform etching using highly directional particles.

[Effect]

In the first and second methods, by forming the surface flat in advance and performing anisotropic etching, it is possible to leave the gate electrode material only on the gate region sandwiched between the originally thick insulating films. It becomes possible. Furthermore, in the third method, due to the shadow effect of anisotropic etching, the gate electrode material can be left only on the gate region behind the insulating film.

〔Example〕

FIG. 1 is a process sectional view showing an embodiment of the present invention. As the semiconductor substrate, for example, a single element semiconductor such as Si may be used, but below, we will use compound semiconductors.
An example using GaAs will be explained. of course,
Other compound semiconductors such as InP can also be used.

First, an n-type impurity, such as Si, is applied to the main surface of a high-resistance GaAs substrate 31 using a 1.2 μm thick photoresist as a mask (not shown in the figure) at an acceleration voltage of 60 keV and a dose of 1×10 ¹² cm ^-2 ion implantation with
A primary injection layer 32 is formed (FIG. 1a). continue,
A silicon nitride film 33 with a thickness of 0.15 μm is coated with plasma.
After depositing on the entire surface by CDV method, a multilayer resist 34 having a structure similar to the three-layer resist 14 with openings only in the portions that will become the source/drain regions,
Formed using reactive ion etching or the like. Using this multilayer resist 34 as a mask, high-density ion implantation of, for example, Si as an n-type impurity is performed at an acceleration voltage of 200 keV and a dose of 4×10 ¹³ cm ^-2 to form a high-density implantation layer 35 (first Figure b). Next, the main surface of the substrate on which the multilayer resist 34 is mounted is covered with SiO ₂ by, for example, a sputter deposition method, and then the SiO ₂ film on the multilayer resist 34 is removed together with the multilayer resist 34 by lift-off.
An SiO ₂ film 36 having a pattern that is an inversion of the pattern of the bottom resist layer of the multilayer resist 34 is formed on the silicon nitride film 33 (FIG. 1c). here,
In order to activate the ion implantation layers 32 and 35,
For example, heat treatment is performed at 800° C. for 20 minutes in a nitrogen atmosphere. Note that there is also a method of avoiding redistribution of implanted ions during activation processing by using laser annealing, flash annealing, or the like that causes less thermal diffusion of ions.

Next, on the main surface of the substrate, a resist pattern (not shown in the figure) having openings only in the portions corresponding to the source and drain electrodes is formed, and using this as a mask, the SiO ₂ film 36 and the silicon nitride film 33 are formed.
Removal by, for example, reactive ion etching and plasma etching, respectively. Next, using the resist pattern, a 0.13μm layer of AuGe/Ni was deposited as an ohmic metal, and then lift and
By turning off and streamlining the remaining parts, a source electrode 37 and a drain electrode 38 are formed (FIG. 1d).

Next, at least the gate region of the silicon nitride film 33 is removed by plasma etching or reactive ion etching using the SiO ₂ film 36 as a mask, thereby removing the primary implantation layer 32.
After exposing the gate electrode material 39, which forms a shot junction with GaAs, is deposited on the main surface of the substrate to flatten the surface (FIG. 1e). In order to deposit the gate electrode material 39 so that the surface is flat, a relatively isotropic deposition method is used in which the deposition rate in the direction perpendicular and parallel to the main surface of the substrate is approximately equal. or SiO ₂ film 3
A deposition method is used in which the deposition rate in the concave gate region sandwiched by the gate electrodes 6 is higher than the deposition rate in the other flat regions. Note that the gate electrode material does not necessarily have to be composed of a single layer and may have a multilayer structure, but in such a case, by using the deposition method described above to form at least one layer, the surface It is possible to make it flat. For example, examples of using relatively isotropic deposition methods include depositing metals such as W and amorphous semiconductors such as Si-Ge-B using the CVD method, and depositing Al, Mo, W, etc. using the sputtering method. There is a method of depositing metals such as or their silicides, or a method of depositing metals such as Ti/Pt/Au and then depositing metals such as Au by a plating method. However, the thickness of the gate electrode material formed by such a relatively isotropic deposition method can be increased by making it thicker than half the opening length of the gate junction portion, that is, the interval between the SiO ₂ films 36 facing each other. , planarize the gate electrode material over the gate region. For example, when the gate opening length is 0.5 μm, the thickness of the gate electrode material may be 0.25 μm or more.

Further, as a deposition method in which the deposition rate in the concave gate region is higher than the deposition rate in the flat region, there is a bias sputtering method in which deposition and etching of the deposited film proceed simultaneously. In this case, the gate electrode material on the gate region can be planarized even if the film thickness is less than half the gate opening length.

After depositing the gate electrode material in this manner, an anisotropic etching method in which the etching rate in the direction perpendicular to the main surface of the substrate is much higher than the etching rate in the parallel direction, such as ion milling, is used.
The gate electrode material is etched by reactive ion etching or reactive ion beam etching.
An amount corresponding to the thickness on the SiO ₂ film 36 is removed.

As a result, a gate electrode 39 ₁ that covers the primary injection layer 31 but does not rise above the SiO ₂ film 36 is formed in a self-aligned manner (FIG. 1f). Incidentally, an unnecessary portion of the remaining gate electrode material 39, for example, a portion 39 ₂ around the ohmic electrode in FIG.
If necessary, although not shown in the figure, it is possible to perform etching removal using at least a resist pattern covering the gate electrode ₃₉₁ on the gate region as a mask.

Next, FIG. 2 is a process sectional view showing another embodiment of the present invention. However, since the steps up to the formation of the source/drain electrodes corresponding to FIG. 1d are the same as those in the above-described embodiment, that portion will be omitted and only the gate electrode forming steps will be shown.

That is, after forming the source/drain electrodes 37 and 38 in the same manner as in the previous embodiment, the primary injection layer 32 is formed.
expose. Next, as the gate electrode material 41 that forms a shot junction with GaAs, a single layer metal such as Al or a multilayer metal such as Ti (bottom layer)/Pt (middle layer)/Au (top layer) is used. , for example, to a thickness of 0.3 μm, is deposited on the main surface of the substrate by vacuum evaporation. Subsequently, an insulating film, such as a silicon nitride film 42, is deposited thereon by an isotropic deposition method, such as a plasma CVD method, and the surface is planarized (FIG. 2a). however,
In order to be planarized, the thickness of the silicon nitride film 42 must be equal to the opening length of the gate junction portion, that is, the thickness of the silicon nitride film 42 must be
It is necessary to make the thickness thicker than half the distance between the SiO ₂ films 36. For example, if the opening length of the gate junction portion is 0.5 μm, the thickness of the silicon nitride film 42 may be 0.25 μm or more. As in the case of depositing the gate electrode material 39 in the embodiment of FIG. 1, a bias sputtering method or the like may be used instead of such an isotropic deposition method.

Subsequently, the silicon nitride film 42 is etched by anisotropic etching, such as reactive ion etching, in which the etching rate in the direction perpendicular to the main surface of the substrate is much higher than the etching rate in the parallel direction.
When etching is performed until the gate electrode material 41 on the SiO ₂ film 36 is exposed, the gate electrode 42 on the gate junction where the silicon nitride film 42 is thicker than on the SiO ₂ film and the SiO ₂ film 36 are etched. Only the peripheral portion ₄₂₂ remains (FIG. 2b). Subsequently, using a resist pattern that covers at least the silicon nitride film 42 on the gate junction, the silicon nitride film 42 ₂ remaining in the peripheral portion of the SiO ₂ film 36 is removed by, for example, reactive ion etching or plasma etching. do. After removing the resist, using the remaining silicon nitride film 42 ₁ as a mask, the gate electrode material 41 other than the gate junction portion is etched away by, for example, ion milling, and the silicon nitride film 42 ₁ is further etched by, for example, plasma etching. By removing the gate electrode material 41 by , the gate electrode material 41 does not rise on the SiO ₂ film 36, and the gate electrode material ₄₁ is removed only at the gate junction.
A self-aligned MESFET structure is obtained (Figure 2c).

In the embodiment shown in FIG. 1, the gate electrode material itself is formed flat, but in this embodiment, another film is used to flatten the surface, so the range of selection of the gate electrode material is widened. In other words, in order to deposit so that the surface is flat, there are limitations on the materials and deposition methods that can be used as long as it is possible to do so and also form a Schottky junction with GaAs, but in this example, the gate electrode material 41 itself is not subject to such severe constraints, but simply
It can be freely selected as an electrode material to form a Schottky junction with GaAs, and the easiest deposition method can be used. On the other hand, any material that can be easily planarized can be selected for the coating.

FIG. 3 is a process sectional view showing still another embodiment of the present invention. However, since the steps up to the formation of the source/drain electrodes corresponding to FIG. 1d are the same as those of the first embodiment described above, they are omitted, and only the gate electrode forming steps are shown.

That is, after forming the source/drain electrodes 37 and 38 in the same manner as described above, the primary injection layer 32 is exposed. Next, a gate electrode material 51 that forms a shot junction with GaAs, such as Al, is then applied.
Single layer metal such as or Ti (bottom layer)/Pt
(middle layer)/Au (top layer)
It is deposited on the main surface of the substrate by vacuum evaporation or sputtering. Next, the gate electrode material deposited on the gate region sandwiched by the SiO ₂ film 36 is etched using a highly directional etching method using particles moving straight in a fixed direction, such as ion milling or reactive ion beam etching. The main surface of the substrate is tilted at an angle θ with respect to the incident direction of the etching particles so that the SiO ₂ film 36 is in the shadow of the incident etching particles (FIG. 3a), and the gate deposited on the SiO ₂ film 36 is Etch until the electrode material is completely removed. As a result, out of the gate electrode material 51,
A MESFET with a gate electrode ₅₁₁ remaining only on the gate region in a self-aligned manner is obtained (FIG. 3b). Note that the angle θ between the normal direction of the main surface of the substrate and the incident direction is determined by l _g being the opening length of the gate region sandwiched between the SiO ₂ films 36, t ₃ being the thickness of the silicon nitride film 33,
When the thickness of the SiO ₂ film 36 is t ₆ and the thickness of the gate electrode material 51 is t ₁ , it is sufficient to satisfy tanθl _g /(t ₃ +t ₆ −t ₁ ), for example, l _g =0.3. μm, t ₃ =
If 0.15μm, t ₆ = 0.5μm, t ₁ = 0.3μm, θ is 40
It can be made larger than the degree. Note that the thickness t ₃ +t ₆ above corresponds to the thickness t ₀ of the insulating film.

In the case of this method, there is no particular restriction on the method of depositing the gate electrode material, and there is no need to form any other film to flatten the surface.

〔Effect of the invention〕

As explained above, according to the present invention, in a self-aligned MESFET, unnecessary stray capacitance of the gate electrode can be eliminated by eliminating the part of the gate electrode material that is built up on the insulating film. A MESFET with superior high frequency and high speed operation can be obtained compared to conventional methods.

[Brief explanation of drawings]

FIG. 1 is a process sectional view showing an embodiment of the present invention;
2 and 3 are process cross-sectional views showing other embodiments of the present invention, and FIGS. 4 and 5 are process cross-sectional views showing a conventional manufacturing method and cross-sections of essential parts for explaining the drawbacks thereof. It is a diagram. 31... High resistance GaAs substrate, 32... Primary implantation layer (active layer), 33, 42, _{42 1} ... Silicon nitride film, 34... Multilayer resist, 35... High density ion implantation layer, 36... SiO ₂ film, 37... Source electrode, 38... Drain electrode, 39, 41, 51
... Gate electrode material, 39 ₁ , 41 ₁ , 51 ₁ ...
gate electrode.

Claims (1)

[Scope of Claims] 1. Consisting of one or more layers including at least one layer of photoresist having openings in source/drain formation regions of a semiconductor active layer formed in a partial region including the main surface of a semiconductor substrate. A step of forming a resist mask, a step of forming a high-density ion implantation layer by performing ion implantation using this resist mask, and a step of forming an insulating film on a semiconductor substrate on which the resist mask is mounted, and then removing this insulating film. A step of leaving only the portion facing the high-density ion-implanted layer and removing the rest along with the resist mask, a heat treatment step of activating the ion-implanted layer, and a source and a part of the high-density ion-implanted layer. forming a drain electrode and a gate electrode in a region sandwiched between the insulating films on the semiconductor active layer; the step of forming the gate electrode includes the step of depositing a gate electrode material on the main surface of the semiconductor; A gate electrode of the film is formed by depositing a film thereon so that the surface is flat, and an anisotropic etching method in which the etching rate is high in the direction perpendicular to the direction parallel to the main surface. etching is performed to planarize the concave region, leaving the film only on the gate region sandwiched between the insulating films; and etching the gate electrode material using the remaining film as a mask, leaving the film only on the gate region. A method for manufacturing a field effect transistor, comprising the step of leaving the gate electrode material. 2. Forming a resist mask composed of one or more layers including at least one layer of photoresist having openings in the source/drain formation regions of the semiconductor active layer formed in a partial region including the main surface of the semiconductor substrate. , a step of forming a high-density ion implantation layer by performing ion implantation using this resist mask, and a step of forming an insulating film on a semiconductor substrate on which the resist mask is mounted, and then implanting the high-density ions in this insulating film. a step of leaving only a portion facing the implanted layer and removing the rest along with the resist mask; a heat treatment step of activating the ion implanted layer; forming a gate electrode in a region sandwiched between the insulating films on the semiconductor active layer; the step of forming the gate electrode includes a step of depositing gate electrode material on the main surface of the semiconductor; etching the gate electrode material using a strong etching method and tilting the main surface of the substrate with respect to the direction of incidence of etching particles, leaving the gate electrode material only on the gate region sandwiched between the insulating films; , θ is the angle at which the main surface of the substrate is inclined with respect to the direction of incidence of etching particles, lg is the opening length of the gate region sandwiched between the insulating films, t ₀ is the thickness of the insulating film, and is the thickness of the gate electrode. A method for manufacturing a field effect transistor, characterized in that the relationship tanθ≧lg/(t ₀ −t ₁ ) is satisfied, where the length is t ₁ .