JPH0358743U - - Google Patents

Info

Publication number
JPH0358743U
JPH0358743U JP6040790U JP6040790U JPH0358743U JP H0358743 U JPH0358743 U JP H0358743U JP 6040790 U JP6040790 U JP 6040790U JP 6040790 U JP6040790 U JP 6040790U JP H0358743 U JPH0358743 U JP H0358743U
Authority
JP
Japan
Prior art keywords
microprocessor
parity
memory
address decoder
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6040790U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP6040790U priority Critical patent/JPH0358743U/ja
Publication of JPH0358743U publication Critical patent/JPH0358743U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
JP6040790U 1989-06-09 1990-06-07 Pending JPH0358743U (OSRAM)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6040790U JPH0358743U (OSRAM) 1989-06-09 1990-06-07

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP6780389 1989-06-09
JP6040790U JPH0358743U (OSRAM) 1989-06-09 1990-06-07

Publications (1)

Publication Number Publication Date
JPH0358743U true JPH0358743U (OSRAM) 1991-06-07

Family

ID=31718233

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6040790U Pending JPH0358743U (OSRAM) 1989-06-09 1990-06-07

Country Status (1)

Country Link
JP (1) JPH0358743U (OSRAM)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998029814A1 (fr) * 1996-12-26 1998-07-09 Rohm Co., Ltd. Carte a circuit integre
WO2002041152A1 (fr) * 2000-11-16 2002-05-23 Niigata Seimitsu Co., Ltd. Système de mémoire
JP2002360338A (ja) * 2001-06-12 2002-12-17 Takashi Kosako 化粧綿
JP5575997B1 (ja) * 2013-03-13 2014-08-20 長瀬産業株式会社 半導体装置及び半導体装置に対するエントリアドレス書き込み／読み出し方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998029814A1 (fr) * 1996-12-26 1998-07-09 Rohm Co., Ltd. Carte a circuit integre
WO2002041152A1 (fr) * 2000-11-16 2002-05-23 Niigata Seimitsu Co., Ltd. Système de mémoire
JP2002360338A (ja) * 2001-06-12 2002-12-17 Takashi Kosako 化粧綿
JP5575997B1 (ja) * 2013-03-13 2014-08-20 長瀬産業株式会社 半導体装置及び半導体装置に対するエントリアドレス書き込み／読み出し方法

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