JPH0358184B2 - - Google Patents

Info

Publication number
JPH0358184B2
JPH0358184B2 JP58031188A JP3118883A JPH0358184B2 JP H0358184 B2 JPH0358184 B2 JP H0358184B2 JP 58031188 A JP58031188 A JP 58031188A JP 3118883 A JP3118883 A JP 3118883A JP H0358184 B2 JPH0358184 B2 JP H0358184B2
Authority
JP
Japan
Prior art keywords
word line
memory cell
node
memory device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58031188A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59155954A (ja
Inventor
Hiroshi Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP58031188A priority Critical patent/JPS59155954A/ja
Priority to US06/580,388 priority patent/US4596003A/en
Publication of JPS59155954A publication Critical patent/JPS59155954A/ja
Publication of JPH0358184B2 publication Critical patent/JPH0358184B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP58031188A 1983-02-24 1983-02-24 半導体メモリ装置 Granted JPS59155954A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP58031188A JPS59155954A (ja) 1983-02-24 1983-02-24 半導体メモリ装置
US06/580,388 US4596003A (en) 1983-02-24 1984-02-15 Semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58031188A JPS59155954A (ja) 1983-02-24 1983-02-24 半導体メモリ装置

Publications (2)

Publication Number Publication Date
JPS59155954A JPS59155954A (ja) 1984-09-05
JPH0358184B2 true JPH0358184B2 (de) 1991-09-04

Family

ID=12324457

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58031188A Granted JPS59155954A (ja) 1983-02-24 1983-02-24 半導体メモリ装置

Country Status (2)

Country Link
US (1) US4596003A (de)
JP (1) JPS59155954A (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6050797A (ja) * 1983-08-31 1985-03-20 Toshiba Corp 半導体記憶装置
US4723228B1 (en) * 1983-08-31 1998-04-21 Texas Instruments Inc Memory decoding circuitry
JPS60109267A (ja) * 1983-11-17 1985-06-14 Fujitsu Ltd スタテイツクｒａｍ
JPS63200391A (ja) * 1987-02-16 1988-08-18 Toshiba Corp スタテイツク型半導体メモリ
JP3026341B2 (ja) * 1987-02-23 2000-03-27 株式会社日立製作所 半導体メモリ装置
US4797858A (en) * 1987-03-30 1989-01-10 Motorola, Inc. Semiconductor memory with divided word lines and shared sense amplifiers
US4910574A (en) * 1987-04-30 1990-03-20 Ibm Corporation Porous circuit macro for semiconductor integrated circuits
US5222047A (en) * 1987-05-15 1993-06-22 Mitsubishi Denki Kabushiki Kaisha Method and apparatus for driving word line in block access memory
US4849904A (en) * 1987-06-19 1989-07-18 International Business Machines Corporation Macro structural arrangement and method for generating macros for VLSI semiconductor circuit devices
KR100213602B1 (ko) * 1988-05-13 1999-08-02 가나이 쓰도무 다이나믹형 반도체 기억장치
JPH02141993A (ja) * 1988-11-21 1990-05-31 Toshiba Corp 半導体記憶装置
JP3058431B2 (ja) * 1990-06-12 2000-07-04 株式会社東芝 半導体記憶装置
JP2994120B2 (ja) * 1991-11-21 1999-12-27 株式会社東芝 半導体記憶装置
JPH10125070A (ja) * 1996-10-23 1998-05-15 Nec Corp メモリ装置
JP4530527B2 (ja) 2000-12-08 2010-08-25 ルネサスエレクトロニクス株式会社 スタティック型半導体記憶装置
JP6091083B2 (ja) * 2011-05-20 2017-03-08 株式会社半導体エネルギー研究所 記憶装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4542485A (en) * 1981-01-14 1985-09-17 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor integrated circuit

Also Published As

Publication number Publication date
JPS59155954A (ja) 1984-09-05
US4596003A (en) 1986-06-17

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