JPH0357635U - - Google Patents

Description

[Brief explanation of the drawing]

A single figure is a circuit diagram illustrating the analog-to-digital portion of a CODEC using an auto-zero loop according to the present invention.

Claims (1)

[Claims of Utility Model Registration] 1. Provides a digital representation of the analog input signal with an output sign bit representing the polarity of the analog input signal and is operable in either power-up mode or normal analog-to-digital conversion mode. In analog-to-digital converter circuits,
an operational amplifier having a first input lead connected to receive an analog input signal to be converted and having a second input lead, an automatic zero loop, and an output signal representative of the current mode of operation of the analog-to-digital converter circuit; A power-up/power-down logic circuit that supplies the D. C. a multi-bandwidth sub-circuit controlled by the power-up/power-down logic circuit to provide a feedback signal to a second input lead of the operational amplifier to cancel offset; operates with a relatively small time constant sufficient to offset circuit offsets during short power-up periods and during the normal analog-to-digital conversion mode of the analog-to-digital converter circuit. The multi-bandwidth subcircuit operates with a relatively large time constant to continuously cancel variable circuit offsets without requiring interruption of normal operation of the converter circuit; An analog-to-digital converter circuit, characterized in that it is obtained by integrating with respect to time a selected voltage corresponding to the value of a bit. 2 Utility Model Registration Claim 1 provides that the multi-bandwidth circuit has a variable impedance RC network, and the variable impedance is controlled by the power-up/power-down logic circuit. Characteristic analog-to-digital converter circuit.