JPH0377531U - - Google Patents
Info
- Publication number
- JPH0377531U JPH0377531U JP13833989U JP13833989U JPH0377531U JP H0377531 U JPH0377531 U JP H0377531U JP 13833989 U JP13833989 U JP 13833989U JP 13833989 U JP13833989 U JP 13833989U JP H0377531 U JPH0377531 U JP H0377531U
- Authority
- JP
- Japan
- Prior art keywords
- section
- signal
- resistor
- clock signal
- appearing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Analogue/Digital Conversion (AREA)
- Manipulation Of Pulses (AREA)
Description
第１図は本考案に係る並列型ＡＤ変換器の一実
施例を示す構成図、第２図は本考案の他の実施例
構成図、第３図は従来の並列型ＡＤ変換器の一例
を示す構成図である。
１０……入力バツフア部、２０……信号比較部
、３０……拡大保持部、５０……デジタル回路、
６０……正帰還回路部、７０……出力バツフア部
、Ｑ１〜Ｑ１９……トランジスタ、ＲＣ，Ｒ１〜
Ｒ５……抵抗。
Fig. 1 is a block diagram showing one embodiment of a parallel AD converter according to the present invention, Fig. 2 is a block diagram showing another embodiment of the present invention, and Fig. 3 is an example of a conventional parallel AD converter. FIG. 10...Input buffer section, 20...Signal comparison section, 30...Enlargement holding section, 50...Digital circuit,
60...Positive feedback circuit section, 70...Output buffer section, Q1 to Q19 ...Transistor, RC, R1 to
R5 ...Resistance.
Claims (1)
ナログ入力電圧と基準電圧が加えられ、各エミツ
タが共通接続されかつクロツク信号がＨＩＧＨレ
ベルのときにオンとなるトランジスタを介して転
電流回路に接続された２つのトランジスタを備え
、クロツク信号がＨＩＧＨレベルのときアナログ
入力電圧を基準電圧と比較すると同時に比較結果
を増幅する信号比較部と、 この信号比較部の抵抗に現われた微小電位差を
それぞれ増幅する正帰還回路部と、 前記信号比較部の抵抗に現われた電圧が各コレ
クタに印加されると共に前記正帰還回路部の各出
力が各ベースに加えられ、かつ共通接続されたエ
ミツタがクロツク信号のＬＯＷレベルのときオン
となるトランジスタを介して定電流回路に接続さ
れた２つのトランジスタを備え、前記信号比較部
の抵抗に現われた電位差に対応するデジタル値を
得る拡大保持部と、 ２つのエミツタフオロワ回路で構成され、前記
拡大保持部に現われたデジタル値に対応した信号
を出力する出力バツフア を具備し、出力バツフアの出力側より混入するパ
ルス性ノイズの拡大保持部への影響を軽減したこ
とを特徴とする並列型ＡＤ変換器の比較器。[Claims for Utility Model Registration] A transistor in which a resistor is connected to each collector, an analog input voltage and a reference voltage are applied to each base, and each emitter is commonly connected and turns on when the clock signal is at HIGH level. A signal comparator section includes two transistors connected to a current transfer circuit via a signal comparator section that compares the analog input voltage with a reference voltage when the clock signal is at a high level, and simultaneously amplifies the comparison result. a positive feedback circuit section for amplifying minute potential differences, respectively; and a voltage appearing in the resistor of the signal comparison section is applied to each collector, and each output of the positive feedback circuit section is applied to each base, and is commonly connected. an enlarged holding section for obtaining a digital value corresponding to the potential difference appearing in the resistor of the signal comparison section, comprising two transistors connected to a constant current circuit via a transistor whose emitter is turned on when the clock signal is at the LOW level; and an output buffer which is composed of two emitter follower circuits and outputs a signal corresponding to the digital value appearing in the enlarged holding section, and which prevents the influence of pulsed noise mixed in from the output side of the output buffer on the enlarged holding section. A comparator for a parallel AD converter, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13833989U JPH0377531U (en) | 1989-11-29 | 1989-11-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13833989U JPH0377531U (en) | 1989-11-29 | 1989-11-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0377531U true JPH0377531U (en) | 1991-08-05 |
Family
ID=31685446
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13833989U Pending JPH0377531U (en) | 1989-11-29 | 1989-11-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0377531U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9138250B2 (en) | 2006-04-24 | 2015-09-22 | Ethicon Endo-Surgery, Inc. | Medical instrument handle and medical instrument having a handle |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5760727A (en) * | 1980-09-26 | 1982-04-12 | Matsushita Electric Ind Co Ltd | Comparator circuit |
| JPS62196919A (en) * | 1986-02-25 | 1987-08-31 | Nec Corp | Comparator |
-
1989
- 1989-11-29 JP JP13833989U patent/JPH0377531U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5760727A (en) * | 1980-09-26 | 1982-04-12 | Matsushita Electric Ind Co Ltd | Comparator circuit |
| JPS62196919A (en) * | 1986-02-25 | 1987-08-31 | Nec Corp | Comparator |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9138250B2 (en) | 2006-04-24 | 2015-09-22 | Ethicon Endo-Surgery, Inc. | Medical instrument handle and medical instrument having a handle |
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