JPS6320262U - - Google Patents
Info
- Publication number
- JPS6320262U JPS6320262U JP11230686U JP11230686U JPS6320262U JP S6320262 U JPS6320262 U JP S6320262U JP 11230686 U JP11230686 U JP 11230686U JP 11230686 U JP11230686 U JP 11230686U JP S6320262 U JPS6320262 U JP S6320262U
- Authority
- JP
- Japan
- Prior art keywords
- voltage value
- input signal
- circuit
- output
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005452 bending Methods 0.000 claims 2
- 230000007423 decrease Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
- Picture Signal Circuits (AREA)
- Control Of Voltage And Current In General (AREA)
Description
第１図は本考案の一実施例の要部を示すブロツ
ク図、第２図および第３図はそれぞれ第１の回路
および第２の回路の回路例、第４図は本実施例の
入出力特性図、第５図は従来の折れ線近似回路の
回路図、第６図は従来の折れ線近似回路の入出力
特性図である。
図において、１……第１の回路、２……第２の
回路、３……折れ線近似回路、４，５，１２〜１
４，２４〜２６……演算増幅器、６，７，２７〜
３０……ダイオード、８，９，１５，３１〜３３
……可変抵抗、１０，１１，１６〜２３，３４〜
３８……抵抗。
FIG. 1 is a block diagram showing the main parts of an embodiment of the present invention, FIGS. 2 and 3 are circuit examples of the first circuit and second circuit, respectively, and FIG. 4 is the input/output of this embodiment. FIG. 5 is a circuit diagram of a conventional polygonal line approximation circuit, and FIG. 6 is an input/output characteristic diagram of a conventional polygonal line approximation circuit. In the figure, 1...first circuit, 2...second circuit, 3...broken line approximation circuit, 4, 5, 12-1
4, 24-26... operational amplifier, 6, 7, 27-
30...Diode, 8, 9, 15, 31-33
...Variable resistance, 10, 11, 16 ~ 23, 34 ~
38...Resistance.
Claims (1)
信号が出力され、前記入力信号が前記下限電圧値
から所定の折曲げ点に対応する電圧値に至るまで
の電圧値に対しては、前記入力信号の電圧値の増
大にともない前記出力信号の電圧値も増大する形
で出力され、前記入力信号が前記折曲げ点に対応
する電圧値から上限電圧値に至るまでの電圧値に
対しては、前記入力信号の電圧値の増大にともな
い前記出力信号の電圧値が減少する形で出力され
て、前記入力信号の電圧値が上限電圧値である時
に０ボルトの出力信号を出力する第１の回路と、 前記入力信号に対して、前記第１の回路の出力
信号を加算また減算する第２の回路と、 を備えることを特徴とする折れ線近似回路。[Claims for Utility Model Registration] An output signal of 0 volts is output with respect to a lower limit voltage value of an input signal, and the voltage at which the input signal reaches a voltage value corresponding to a predetermined bending point from the lower limit voltage value. With respect to the voltage value, as the voltage value of the input signal increases, the voltage value of the output signal also increases, and the input signal reaches the upper limit voltage value from the voltage value corresponding to the bending point. For a voltage value of , the voltage value of the output signal decreases as the voltage value of the input signal increases, and when the voltage value of the input signal is the upper limit voltage value, an output of 0 volts A polygonal line approximation circuit comprising: a first circuit that outputs a signal; and a second circuit that adds or subtracts an output signal of the first circuit to or from the input signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11230686U JPS6320262U (en) | 1986-07-21 | 1986-07-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11230686U JPS6320262U (en) | 1986-07-21 | 1986-07-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6320262U true JPS6320262U (en) | 1988-02-10 |
Family
ID=30993054
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11230686U Pending JPS6320262U (en) | 1986-07-21 | 1986-07-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6320262U (en) |
-
1986
- 1986-07-21 JP JP11230686U patent/JPS6320262U/ja active Pending
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