JPS62196474U - - Google Patents
Info
- Publication number
- JPS62196474U JPS62196474U JP8397686U JP8397686U JPS62196474U JP S62196474 U JPS62196474 U JP S62196474U JP 8397686 U JP8397686 U JP 8397686U JP 8397686 U JP8397686 U JP 8397686U JP S62196474 U JPS62196474 U JP S62196474U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- peak
- video signal
- response characteristics
- peak value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000284 extract Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 1
Landscapes
- Television Receiver Circuits (AREA)
Description
第１図は本考案の一例の構成図、第２図はその
説明のための図、第３図〜第５図は従来の技術の
説明のための図である。
１は入力端子、２，１２はトランジスタ、３は
電源端子、４，５，１４は抵抗器、６は演算増幅
器、７，１３は電圧源、８，１１はコンデンサ、
９，１０はダイオード、１５は出力端子である。
FIG. 1 is a block diagram of an example of the present invention, FIG. 2 is a diagram for explaining the same, and FIGS. 3 to 5 are diagrams for explaining the conventional technology. 1 is an input terminal, 2 and 12 are transistors, 3 is a power supply terminal, 4, 5, and 14 are resistors, 6 is an operational amplifier, 7 and 13 are voltage sources, 8 and 11 are capacitors,
9 and 10 are diodes, and 15 is an output terminal.
Claims (1)
する回路を介して取出して映像信号の利得制御を
行うようにしたピークＡＢＬ回路において、 上記所定の応答特性を有する回路の出力側に所
定の不感領域の設けられた回路を挿入したことを
特徴とするピークＡＢＬ回路。[Claims for Utility Model Registration] A peak ABL circuit that detects the peak value of an input video signal and extracts the detected peak value through a circuit having predetermined response characteristics to perform gain control of the video signal. A peak ABL circuit characterized in that a circuit provided with a predetermined dead area is inserted on the output side of the circuit having the predetermined response characteristics.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986083976U JPH0628862Y2 (en) | 1986-06-02 | 1986-06-02 | Peak ABL circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986083976U JPH0628862Y2 (en) | 1986-06-02 | 1986-06-02 | Peak ABL circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62196474U true JPS62196474U (en) | 1987-12-14 |
| JPH0628862Y2 JPH0628862Y2 (en) | 1994-08-03 |
Family
ID=30938060
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986083976U Expired - Lifetime JPH0628862Y2 (en) | 1986-06-02 | 1986-06-02 | Peak ABL circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0628862Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60236378A (en) * | 1984-04-26 | 1985-11-25 | アールシーエー トムソン ライセンシング コーポレイシヨン | Controller in video signal processor |
-
1986
- 1986-06-02 JP JP1986083976U patent/JPH0628862Y2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60236378A (en) * | 1984-04-26 | 1985-11-25 | アールシーエー トムソン ライセンシング コーポレイシヨン | Controller in video signal processor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0628862Y2 (en) | 1994-08-03 |