JPH0350U - - Google Patents
Info
- Publication number
- JPH0350U JPH0350U JP5736489U JP5736489U JPH0350U JP H0350 U JPH0350 U JP H0350U JP 5736489 U JP5736489 U JP 5736489U JP 5736489 U JP5736489 U JP 5736489U JP H0350 U JPH0350 U JP H0350U
- Authority
- JP
- Japan
- Prior art keywords
- lead
- tip
- semiconductor element
- inner lead
- fringe
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 10
- 239000011347 resin Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000003848 UV Light-Curing Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第1図aおよび第1図bは本考案実施例の半導
体装置用リードフレームを示す図、第2図a乃至
第2図dは本考案実施例の半導体装置用リードフ
レームの製造工程を示す図、第3図は本考案実施
例の半導体装置用リードフレームを用いた半導体
装置の実装例を示す図である。 1…リードフレーム、2…放熱板、2a…凸部
、2b…フリンジ部、3…半導体素子、4…イン
ナーリード、5…ボンデイングワイヤ、6…樹脂
、7…タイバー、8…アウターリード、F…紫外
線硬化樹脂。
体装置用リードフレームを示す図、第2図a乃至
第2図dは本考案実施例の半導体装置用リードフ
レームの製造工程を示す図、第3図は本考案実施
例の半導体装置用リードフレームを用いた半導体
装置の実装例を示す図である。 1…リードフレーム、2…放熱板、2a…凸部
、2b…フリンジ部、3…半導体素子、4…イン
ナーリード、5…ボンデイングワイヤ、6…樹脂
、7…タイバー、8…アウターリード、F…紫外
線硬化樹脂。
Claims (1)
- 【実用新案登録請求の範囲】 (1) インナーリードおよびこれに連設されるア
ウターリードとを含むリード部と、 該インナーリードの先端に囲まれた領域に半導
体素子を搭載するための凸部および該リード部形
成面よりも下方に位置し、かつインナーリード先
端に囲まれた領域よりも外縁が外側にくるように
形成されたフリンジ部とを有する半導体素子搭載
部とを具備したことを特徴とする半導体装置用リ
ードフレーム。 (2) 前記インナーリードの先端を、前記フリン
ジ部に絶縁性樹脂を介して固着することにより、
前記リード部と前記半導体素子搭載部とが接合せ
しめられていることを特徴とする請求項(1)記載
の半導体装置用リードフレーム。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5736489U JPH0350U (ja) | 1989-05-18 | 1989-05-18 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5736489U JPH0350U (ja) | 1989-05-18 | 1989-05-18 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0350U true JPH0350U (ja) | 1991-01-07 |
Family
ID=31582000
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5736489U Pending JPH0350U (ja) | 1989-05-18 | 1989-05-18 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0350U (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51161148U (ja) * | 1975-06-16 | 1976-12-22 | ||
US9873140B2 (en) | 2011-09-16 | 2018-01-23 | Nabtesco Corporation | Foreign material removing device of track turnout portion |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59207645A (ja) * | 1983-05-11 | 1984-11-24 | Toshiba Corp | 半導体装置およびリ−ドフレ−ム |
-
1989
- 1989-05-18 JP JP5736489U patent/JPH0350U/ja active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59207645A (ja) * | 1983-05-11 | 1984-11-24 | Toshiba Corp | 半導体装置およびリ−ドフレ−ム |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51161148U (ja) * | 1975-06-16 | 1976-12-22 | ||
US9873140B2 (en) | 2011-09-16 | 2018-01-23 | Nabtesco Corporation | Foreign material removing device of track turnout portion |