JPH0350741A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To sufficiently preform annealing process for activating a source and a drain by performing self aligning process for determining the length of a channel before aluminum of a gate is formed. CONSTITUTION:After an insulating film 2 is formed on silicon wafer 1, a polysilicon layer 3 is stacked. Phosphorus, boron, arsenic, etc., are contained in the above polysilicon. Photo patterning and etching are performed in the manner in which the polysilicon is entirely removed except on a source, a drain, a gate, and wiring. After resist is eliminated, a silicon nitride film 4 is formed. An aperture is formed in a part turning to a channel; resist 5 is exfoliated by etching elimination; then a gate oxide film 6 is formed. By annealing process, impurity contained in the polysilicon is diffused into the silicon substrate, thereby forming a source and drain 7. On the source and drain, an aperture 8 is formed in the silicon nitride film 4, and an aluminum layer wiring 9 and a gate 10 are formed. By this method, the chip area can be reduce as the result of high density integration of transistors by self alignment.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing an MO3 type transistor having an aluminum gate and using a self-line method.

[Prior Art] A conventional method for manufacturing an aluminum gate self-line MO3) transistor is as shown in FIG. That is, the source/drain 7 is formed in advance and the gate 10 is patterned. At this time, the source
The drain and gate are formed slightly apart. Next, an impurity 13 of the same type as the source/drain (P or N type) is introduced into the silicon substrate 1 by ion implantation into the aluminum of the gate via a self-alignment line. Therefore, the source/drain consists of a high concentration region previously formed by diffusion and a low concentration region created by ion implantation.

[Problems to be Solved by the Invention] However, in the conventional transistor formation method, the self-line process for determining the channel length is performed after forming the aluminum gate, so it is not sufficient to activate the low-concentration source and drain. The drain resistance increases and the transistor current drive ability becomes insufficient (
However, there is a problem in that the channel width is increased (or the direct injection of the chip becomes wider due to the use of non-self-line transistors).

[Means for Solving the Problems] A method for manufacturing a MOS (MOS) gingister according to the present invention includes steps of α) forming a polysilicon layer containing impurities to be diffused into the source/drain, and b) forming the polysilicon layer with only the gate portion remaining. c) forming a silicon nitride film; d) photo-etching the nitride film and polysilicon to open only the gate area; and g) forming an opening. f) a step of diffusing impurities contained in polysilicon into the substrate by annealing to form a source/drain; g) a step of photo-etching the silicon nitride film; and h) a step of photo-etching the silicon nitride film. and i) photo-etching the aluminum film to form gates and wiring.

[Example] FIG. 1 is a cross-sectional view showing an example of the present invention. After forming an element isolation insulating film 2 (LOOO3) with a thickness of 0.7 to 2.0 pm on a silicon wafer 1, a polysilicon layer is formed. 3
pile up. This polysilicon contains impurities (phosphorus, boron, etc.) that will become the IK source and drain.

Arsenic, etc.) is incorporated by ion implantation or thermal diffusion.

Alternatively, impurities may already be included when forming polysilicon. Then the source ° on the drain, on the gate,
Seven-touch patterning and etching are performed so as to leave polysilicon on each wiring and remove it from other areas. After removing the resist using hot sulfuric acid or the like, a silicon nitride film 4 is formed.

This film functions as a mask that defines a channel region with self-alignment lines for the source and drain, and as an interlayer insulating film that separates the metal wiring and polysilicon. A gate oxide film 6 is formed after the resist 5 used to open and remove the channel is peeled off. At this time, the impurity contained in the polysilicon should be
Oxidation is carried out below 0°C. Impurities contained in polysilicon are diffused into the silicon substrate by annealing using a heat treatment furnace or lamp. The source/drain 7 is now formed. Next, holes 8 are made in the silicon nitride film above the contacts on the source and drain, and finally, aluminum or silicon-containing aluminum is deposited or sputtered. This aluminum layer is buttered and etched, and the wiring 9 and the gate 10 are formed. form.

[Effects of the Invention] As described above, according to the method of manufacturing an aluminum gate MOS transistor of the present invention, (1) the chip area can be reduced by increasing the integration of the transistor by self-line (2) the source・By fully activating the drain, it is now possible to obtain a transistor with superior drive capability compared to conventional transistors. (3) All source and drain contacts use polysilicon, which reduces contact resistance, which is often a problem with miniaturization. It has the effect of avoiding the problem of thickening.

[Brief explanation of drawings]

Figure 1 (cL) - (() is the aluminum game of the present invention) MO
! 3) A diagram showing a method of manufacturing a transistor. FIGS. 2(α) to 2(y) are diagrams showing a conventional method of manufacturing an aluminum gate MoS transistor. 1... Silicon substrate 2... Inter-element insulating film (LOOO8) 6.
......Polysilicon film 4...Silicon nitride film 5...Resist 6...Gate film 7...・・・・・・Source conflict drain 8・・・・・・
... Contact hole 9 ... River ... Aluminum wiring 10 ... ... Aluminum gate 11 ...
...Field oxide film 12...
Field oxide film 13...Low concentration source, drain Figure 2 Figure 2

Claims (1)

[Claims] (1) a) a step of forming a polysilicon layer containing impurities to be diffused into the source/drain; and b) a step of photo-etching the polysilicon into a desired pattern, leaving only the gate area. c) Step of forming a silicon nitride film; d) Step of photo-etching to open the nitride film and polysilicon only in the gate region; e) Step of oxidizing the gate only in the opening; and f) Annealing process to include in the polysilicon. g) photo-etching the silicon nitride film; h) forming aluminum or aluminum containing silicon or copper; and i) forming the aluminum film. A method for manufacturing a semiconductor device, characterized by forming gates and wiring by photo-etching.