JPH0349411A - Cmos latch circuit with reset - Google Patents

Abstract

PURPOSE:To decrease the number of circuit elements by three elements and to simplify a wiring pattern by using an inverter and 9 MOS transistors. CONSTITUTION:A CMOS latch circuit is composed of an inverter 1, first conductive type 1st-3rd MOS transistors Q1-Q3, second conductive type 4th and 5th MOS transistors Q4 and Q5, second conductive type 6th MOS transistor Q6, first conductive type 7th and 8th MOS transistors Q7 and Q8 and second conductive type 9th MOS transistor Q9. Thus, an area to be occupied by the element and wiring pattern can be reduced and a chip size can be made compact.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a CMOS latch circuit, and more particularly to a CMOS latch circuit with reset.

[Prior Art] Conventionally, this type of latch circuit has been configured as shown in FIG.

That is, between the second power supply v0° and the first power supply Vss, there is a P-channel MO8F ETQ23. Q22 and N-channel MO8FET Q21. Q20 are connected in series. Also, a second power source V. 0 and the above P channel MO8
The above P channel M is connected between the drain of FET022 and
OS FET Q21. P-channel MOSFET Q2 in parallel with Q2□? -Q28 are connected in series.

Furthermore, between the drain of the N-channel MO8FET Q2+3 and the first power supply VSS, the N-channel MO8FE
TQ28. N-channel MOS F E in parallel with Q20
T Q2+5. Q24 is connected in series.

MOS FET Q20. A data input signal is input to each gate of Q23. Also, MO8F
ETQ21. A first gate input signal G is input to each gate of Q2G. Furthermore, MO8FETQ2□, Q
A second gate input signal G is input to each of the 26 gates.

On the other hand, the commonly connected MOS FET Q 21
．． Each drain of Q 22°Q 251 Q 2'a is connected to one input terminal of the NOR gate 2. Further, the other input terminal of this NOR gate 2 receives a resetting/resetting input signal R. The output signal of this NOR gate 2 is output as a data output signal Q, and the output signal of MO3FETQ24. It is supplied to each gate of Q27 and the input terminal of the inverter 3. The output of inverter 3 is output as data output signal Q.

Next, the operation of the CMOS latch circuit configured as described above will be explained.

Now, the first gate input signal G is
When the gate input signal G is “L” and the data input signal is taken in, the data input signal is input to the CM of the first stage.
Inverted by OS inverter and further NOR gate 2
The signal returns to the same phase again through the signal and is output as the data output signal Q.

Next, when the first gate input signal G changes to “L” and the second gate input signal G changes to “IIH”, the MO8FETQ25
．． Q2B both turn on, MO8FETQ 241 Q
Since the data output signal Q is positively fed back to 27 via the NOR gate 2, the data output signal Q is held as it is.

The first gate input signal G is 111. II. When the second gate input signal G is 'H', the reset input signal R is 'H'.
When the signal becomes "H", the output of the NOR gate 2, that is, the data output signal Q becomes "L".

Even in this case, MOS FET Q 24. Q
Since positive feedback is applied to 27 via NOR gate 2,
The data output signal Q is held at L''.

[Problems to be Solved by the Invention] The conventional CMOS latch circuit described above has a NOR gate 2
Since the latch circuit is made up of four elements and the inverter 3 is made up of two elements, a total of 14 elements are required, which is a large number of elements, and there is a problem that the chip size increases when a large number of latch circuits are integrated.

Furthermore, in the conventional CMOS latch circuit, the wiring for the first gate input signal is connected to the N-channel MO8FETQ21 and the P-channel MO8FETQ2. The wiring for the second gate input signal is connected to the gate of N-channel MO8FETQ21.
It is connected to the gate of S and P channel MO8FETQ2□. Therefore, as shown in FIG.
The problem is that wiring for the first and second gate input signals must be provided in the channel MO8 region and the N-channel MO8 region, respectively, and the area occupied by the wiring pattern increases, which also increases the chip size. There was a point.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a CMOS latch circuit with reset, which can reduce the number of elements and the area occupied by wiring patterns, thereby reducing the chip size.

[Means for Solving the Problems] A CMOS latch circuit with reset according to the present invention includes an inverter connected between an inverted data output terminal and a data output terminal, and an inverted data output terminal and a first power supply terminal. a first gate input signal, connected in series between the gates, respectively;
First, second and third MO8 transistors of a first conductivity type which input a data input signal and a reset input signal are connected in series between a second power supply terminal and the inverted data output terminal, and have gates connected to the transistors. fourth and fifth MOSs of the second conductivity type that input the data input signal and the second gate input signal, respectively;
a sixth MOS transistor of a second conductivity type connected between the second power supply terminal and the inverted data output terminal and inputting a reset input signal to its gate; seventh and eighth MO8 transistors of a first conductivity type connected in series between the first power supply terminal and the second gate input signal and the output signal of the inverter, respectively; a ninth M of a second conductivity type connected between a power supply terminal and the inverted data output terminal and inputting the output signal of the inverter to its gate;
It is characterized by comprising an OS transistor.

[Operation] When the third MOS transistor driven by the reset input signal is in the on state, when the first and fifth MO3 transistors are turned on by the first and second gate input signals, the first stage CMOS inverter is turned on. It works,
A data input signal is captured and inverted. Furthermore, the output is returned to the same phase by an inverter and output as a data output signal.

When the first and fifth MOS transistors are turned off by the first and second gate input signals, the seventh MOS transistor
8 transistors are turned on, and the 8th and 9th MO
Positive feedback of the data output signal to the gate of the 8 transistor causes the data output signal to be held.

On the other hand, when the sixth MOS transistor is turned on by the reset input signal, the inverted data output terminal is forcibly reset to the second power supply level, and the data output terminal is forcibly reset to the first power supply level.

As described above, according to the present invention, the number of circuit elements can be reduced by three elements compared to the conventional one, and the wiring for gate input signals is also reduced by one wire each in the P-channel MO3 region and the N-channel O8 region. It would be better to have each book separately.

[Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 shows a CMO with reset according to the first embodiment of the present invention.
FIG. 2 is a circuit diagram showing the configuration of an S latch circuit.

Between the second power supply v0° and the first power supply VSS, a P-channel MO8FET Q4. Q5 and N channel MO8F
ETQI Q21 Q3 are connected in series. There is an N between the commonly connected drains of MOS FET Q = , Q5 and the first power supply VSS.
Channel MO8FETQ7 and N-channel MO8FET
Qa and Qa are connected in series. Also, the second power supply■.

. and the MQSFETQ1. Between the commonly connected drains of Qa, there is a P-channel MOSFET Q
e and a P-channel MO8 transistor Q8 are connected in parallel.

A data input signal is input to each gate of MOS FET Q 2 and Q 4 . MO8FET
A first gate input signal G is input to the gate of Q. Also, Mo8FETQ5. A second gate input signal G is input to each gate of Q7. Furthermore, M
A reset input signal R is input to each gate of OS FET Q3 and Qa.

On the other hand, the commonly connected Mo5FETQ1. QI51Qo
, Q? , Q9 are connected to the input terminal of the inverter 1. The input signal to this inverter 1 is taken out as a data output signal Q. Further, the output signal of this inverter 1 is outputted as a data output signal Q, and is also supplied to each gate of Mo5FETQ1 and Qa.

Next, the CMOS according to this embodiment configured as described above
The operation of the latch circuit will be explained with reference to FIG.

First, it is assumed that the reset input signal R is "l" (II), the data input signal is "L", and the data output signal Q is "H". At this time, Mo8FETQ3°Q4=Qa is on, Mo8FETQ2, Qe .

Q8 is off.

When the first gate input signal G becomes "HII" and the second gate input signal G becomes "LII" at time t1, the Mo8FET
Q11 Q10 turns on, so MO8FE T Q
4, power supply voltage V through Qa. 0 is added to the input of inverter 1, the input potential of inverter 1 rises, and at time t2, the output of inverter 1 is inverted to "L u", Mo8FETQ9 is turned on, and MO8FETQ is turned off.As a result, inverter 1 The data output signal Q which is the input of is held at vo., and the data output signal Q is 0[V
held in place.

At time t3, the first gate input signal G becomes
When the gate input signal G of the MO8FET becomes “H11”, the MO8FET
Q1. Qa is off and MO8FETQ7 is on, but
Since MO8FETQa remains off and MO8FETQs remains on, data output signals Q and Q are respectively vcc and
Continues to be held at 0 [V].

Next, at time t4, the data input signal G becomes "HII", and at time t+s, the first gate input signal G becomes "H" again, and the second gate input signal G becomes "HII".
When the gate input signal G of MOS F becomes “L”,
E T Q 1. Since Q5 is turned on, MO8FE
MO8Ii'ETQI,Q2 through TQe.

Current flows through Q3. Here, MO8FETQ.

Q2. The total value of on-resistance of Q3 is MO3Ii”ETQ
If the on-resistance value of 8 is set to approximately 173 or less, at time t8, the input of inverter 1 reaches the input voltage V at which the output voltage is inverted, as shown by the input/output characteristic curve in FIG.
, will be lower than. Therefore, the data output signal Q output from inverter 1 is inverted and becomes "H", and MO8
FET Qe is turned off and the data output signal Q, which is the input of the inverter 1, falls to O[V, and the data output signal Q is held at "Hoo)".

When the first gate input signal G is inverted to "L" and the second gate input signal G is "H" at time t7, the MOS F
E T Q > -Ql is turned off and MO8FETQ7 is turned on. At this time, since MO8FETQg is on, the data output signal Q which is the input of inverter 1
continues to hold 0 [■].

Furthermore, when the reset input signal R becomes "L II" at time t8, MO8FETQ=1 turns off, and MOSFETQ
e turns on. At this time, MO8FETQ7.

Since Q8 is on, the on-resistance value of MO8FETQo is MO8FETQ? , Qa is set to approximately 1/3 of the total on-resistance value of Qa, the input of inverter 1 becomes higher than the input/output voltage v2 in FIG. 3 at time t9, so the output data output from inverter 1 The signal Q is
It reversed and became 111.11, MOSFET
Qe is on and MO8FETQ8 is off. As a result, the data output signal Q, which is the input of the inverter 1, becomes vo.

Also, the data output signal Q is held at 0 [v].

Next, the layout of a chip using the CMOS latch circuit according to this embodiment, particularly the state of gate input wiring, will be explained with reference to FIG. In this embodiment, the wiring for the first gate input signal G is connected to an N-channel MO8FE.
Since it is input only to the gate of TQ, P-channel MO
It is not necessary for area 8. In addition, the second gate input signal G
The wiring is P channel MOS FET Q IS
is connected to the gate of P-channel MO8FET Q7, so on the chip there is a second
It is sufficient to provide one gate input wiring for the gate input line and connect it to the N-channel MO8 region by appropriately extending it inside the chip.

FIG. 5 is a circuit diagram of a CMOS latch circuit according to a second embodiment of the present invention.

This embodiment differs from the first embodiment described above in that MO8FETQ4. Q6 out of Qel is the second '!
(t fRV c The point placed on the c side and the inverter 1
M connected in series between the input terminal of and the first power supply Vss
Among the O8FETs Qs, Q2, and Q, Q3 is arranged on the input end side of the inverter 1, and the data output signal Q is taken out from the input end of the inverter 1 via the inverter 4.

Since the other configurations are similar to the circuit shown in FIG. 1, the same components as in FIG. 1 are given the same reference numerals and detailed explanations will be omitted.

The basic operation of this embodiment is the same as that of the first embodiment, and it is clear that the effects of the present invention can be achieved as in the previous embodiment.

Furthermore, the pulse width of the “L” level of the reset input signal R,
The gate input signal G becomes “HII” after the pulse width of the “)I IT level of the gate input signal G, the pulse width of the “L” level of the gate input signal G, and the data input signal change.
from “l” to “II”, and the gate input signal G is “L”
The data setting time for changing from "H" to "H" is the time from each input until the inverter 1 changes. Therefore, when the fan-out of the inverter 1 is large, the load capacity becomes large and the switching time of the inverter 1 becomes long.

However, according to this embodiment, since the data output signal Q is extracted through two stages of inverters, the inverter 1 switches without being affected by the load of the data output signal Q at all. Therefore, even if the load on the data output Q is large, the pulse width of the "1" level of the reset input signal R, the pulse width of the "IIH" level of the gate input signal G, the pulse width of the "L II" level of the gate input signal G, etc. This has the effect of shortening the width and data setting time of the data input signal.

In addition, a buffer formed by connecting two stages of inverters in series may be connected to the input of inverter 1 to take out the data output signal Q, or the input of inverter 4 or inverter 1 may be
The data output signal Q may be taken out by connecting one inverter to the output of the inverter.

Furthermore, in each of the embodiments described above, MO8FE T
Q4, Qa, Qo, Qs are P channel type, M
oSFETQl, Q2. Q3. Although Ql and Q8 have been explained as N-channel types, the former group can also be referred to as N-channel types.
The latter group may be of P-channel type. In this case, when the power supply voltage Vcc is applied to the inverter 1 via MO8FETQ4 and Q5, MO8FETQ7
Since MO8FETQ4 and Q6 are turned off, the elements of MO8FETQ4 and Q6 can be made smaller, and the input capacitance is also reduced.

[Effects of the Invention] As explained above, according to the present invention, the number of circuit elements can be reduced by three elements (20%) compared to the conventional one. In addition, the wiring of the gate input signal is also
There can be one each in the O8 region and the N-channel MO8 region, and the wiring pattern can be simplified. Therefore, the chip size can be reduced by about 30%.

Further, the present invention has the effect that a high-speed CMOS latch circuit can be provided by reducing the wiring capacitance of the gate input signal line.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a CMOS latch circuit according to the first embodiment of the present invention, Fig. 2 is a timing diagram showing the operation of the latch circuit, and Fig. 3 is a characteristic diagram showing the input/output characteristics of the latch circuit. , FIG. 4 is a plan view showing the wiring layout of the latch circuit, FIG. 5 is a circuit diagram of a CMOS latch circuit according to a second embodiment of the present invention, and FIG. 6 is a circuit diagram of a conventional CMOS latch circuit. FIG. 7 is a plan view showing the wiring layout of the latch circuit shown in FIG. 6. 1.3.4; Inverter, 2; NOR gate, Ql to Q 3 * Ql + Qa * Q2o * Q211
Q241Q2. ;N-channel MO8FET1Q4 to Q. . Q9. Q2□+ Q231 Q2BI Q11? ;P
channel MOSFET

Claims (1)

[Claims] (1) An inverter connected between an inverted data output terminal and a data output terminal, an inverter connected in series between the inverted data output terminal and a first power supply terminal, and a first gate input signal applied to each gate. , are connected in series between first, second and third MOS transistors of a first conductivity type that input a data input signal and a reset input signal, a second power supply terminal and the inverted data output terminal, and a gate fourth and fifth MOS transistors of a second conductivity type that input a data input signal and a second gate input signal, respectively, and connected between the second power supply terminal and the inverted data output terminal; A sixth MOS transistor of a second conductivity type is connected in series between the inverted data output terminal and the first power supply terminal, and has a second gate input signal and a second gate input signal input to the gate, respectively. seventh and eighth MOS transistors of a first conductivity type that input an output signal of the inverter;
connected between the power supply terminal of and the inverted data output terminal,
A CMOS latch circuit with reset, comprising: a ninth MOS transistor of a second conductivity type whose gate receives an output signal of the inverter.