JPH0376560B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a dynamic shift circuit, and more particularly to a dynamic shift circuit constructed of a CMIS circuit and operable by a single clock pulse.

(2) Background of the technology In recent years, the number of LSI circuits such as semiconductor memories or microcomputers that use the CMIS process to save power has increased. However, the CMIS circuit is N-MIS or P-
Compared to single-channel circuits such as MIS, it requires about twice or three times the number of elements or circuit area, and as a result, the overall size of the chip tends to increase. In order to miniaturize the CMIS circuit, it is effective to make the internal circuit a dynamic circuit, especially in recent LSIs such as microcomputers.
It is necessary to make effective use of the fact that its internal circuit is composed of synchronous circuits.

(3) Prior art and problems Figure 1a shows a conventional transfer gate constructed using the CMIS process. This circuit consists of N channels that are turned on and off by clocks φ and φ, which are opposite in phase to each other, as shown in FIG. 1a.
It includes a circuit in which an MIS transistor 1 and a P-channel MIS transistor 2 are connected in parallel, and an inverter 3 that operates as a buffer amplifier. and,
The input signal IN is output through transistors 1 and 2 and inverter 3, which are turned on by clock signals φ and
An output signal OUT synchronized with and is obtained.

FIG. 2a shows a conventional shift circuit constructed by cascading two of the above-mentioned transfer gates and used to construct a circuit such as a shift register or a counter. The circuit in the figure includes a first-stage transfer gate composed of an N-channel MIS transistor 4, a P-channel MIS transistor 5, and an inverter 6, and a first-stage transfer gate composed of an N-channel MIS transistor 7, a P-channel MIS transistor 8, and an inverter 9. It includes a next-stage transfer gate. Transistors 4 and 5 of the first-stage transfer gate are driven by clocks φ _A and _A of mutually opposite phase shown in FIG. 2b, respectively, and transistors 7 and 8 of the next-stage transfer gate are driven by the clocks φ A and A shown in FIG. 2b, respectively. It is driven by clocks _φB and _B that are in opposite phases to each other. Clocks φ _B and _B that are delayed from clocks φ _A and _A by, for example, 1/2 cycle are used. The input signal IN used for the first stage inverter passes through transistors 4 and 5 controlled by clocks φ _A and _A and is accumulated in the stray capacitance present in the input circuit of inverter 6. The signal accumulated in the stray capacitance is inputted to the next-stage transfer gate via inverter 6, passes through the transfer gate at the timing of clocks φ _B and _B , and is taken out from inverter 9 as output signal OUT.

FIG. 3 shows a circuit called a clock gate, which is constructed by connecting two N-channel MIS transistors 10, 11 and two P-channel MIS transistors 12, 13 in series between the power supply _Vcc and the ground. be done. The input signal IN is applied to the gates of transistors 11 and 12, and the output signal
OUT is taken from the common drain of these transistors 11 and 12. The gates of transistors 10 and 13 are respectively applied with clocks φ and having opposite phases shown in FIG. 1B. In the circuit of FIG. 3, when the clock φ is at a high level and the clock is at a low level, transistors 10 and 13 are both turned on, and the input signal IN is inverted and output as the output signal OUT.

A disadvantage of each of the conventional circuits described above is that they require two types of clocks that are opposite in phase or complementary to each other. Furthermore, when constructing a circuit such as a shift register or a counter using the above-mentioned transfer gate or clock gate, two sets of clocks having mutually opposite phases as shown in FIG. 2b are used, resulting in a total of four types of clock signals. I need. Furthermore, it is necessary that the clocks having opposite phases to each other are so-called non-overlapping clocks, and therefore it is necessary that the clocks having opposite phases to each other do not both go to a high level or a low level at the same time. However, with non-overlapping clocks, the higher the clock frequency and the higher the duty cycle of the clock is 50
%, the more susceptible it is to circuit delays and the more difficult it becomes to create.

(4) Purpose of the Invention In view of the problems with the conventional type described above, the purpose of the present invention is to reduce the number of types of clocks required in a CMIS-type dynamic shift circuit by operating the shift circuit with a single clock. The objective is to improve the reliability of operation.

(5) Structure of the invention According to the present invention, the first and second PPSs whose sources are respectively connected to the first power source
a first N-channel MIS transistor whose gate and drain are commonly connected to the first P-channel MIS transistor; and a second N-channel MIS transistor whose gate and drain are commonly connected to the second P-channel MIS transistor. an N-channel MIS transistor, and a second N-channel MIS transistor.
a third N-channel MIS transistor connected between the transistor and the second power supply;
connecting the drain of the P-channel MIS transistor to the gate of the second P-channel transistor;
the first P-channel MIS transistor;
Applying a clock pulse to the gate of the third N-channel MIS transistor,
This is achieved by providing a dynamic shift circuit characterized in that the source of the transistor is used as an input terminal, and the drain of the second P-channel MIS transistor is used as an output terminal.

(6) Examples of the invention Examples of the invention will be described below with reference to the drawings. FIG. 4a shows a dynamic shift circuit according to one embodiment of the present invention. The circuit shown in the figure has an initial stage consisting of an N-channel MIS transistor 41 and a P-channel MIS transistor 42 connected in series.
CMIS circuit and N-channel CMIS transistors 43 and 44 connected in series between power supply V _cc and ground.
and a next-stage CMIS circuit consisting of a P-channel MIS transistor 45, etc. transistor 42
The source of transistor 4 is connected to the power supply V _cc and
The input signal IN is applied to the source of 1. Also,
Clock pulse φ is applied to the gates of transistors 42, 41 and 43. transistor 42
and 41 drains are commonly connected to the first stage CMIS
It is taken out as the output A of the circuit and input to the gates of transistors 44 and 45 of the next stage CMIS circuit. The output OUT of the next stage CMIS circuit is taken out from the commonly connected drains of transistors 44 and 45.

FIG. 4b shows the circuit shown in FIG.
An equivalent circuit using a phase clock is shown. That is, the equivalent circuit in the figure is the inverter 46
, an N-channel MIS transistor 47 and a P-channel MIS transistor 47 driven by a two-phase clock φ and
It is constituted by a parallel circuit with MIS transistor 8.

Next, the operation of the circuit shown in FIG. 4a will be explained using FIG. If input IN is low level, first stage
The CMIS circuit becomes equivalent to the CMIS inverter and reaches point A.
A signal obtained by inverting the clock pulse φ is output. In this case, during the period when the clock pulse φ is at a high level, the transistor 43 of the next stage CMIS circuit is turned on, and since the level at point A is low, the transistor 45 is turned on and the transistor 44 is turned off, so that the output OUT is at a high level. Become. During the low level period of the clock pulse φ, the transistor 43 is turned off and the level at point A becomes high level, so the transistor 45 is also turned off, so that the output
As shown by signal Z in FIG. 5, OUT enters a high impedance state, that is, a floating state, and maintains the level of the previous period. Therefore, the output OUT remains high from the first rising edge of the clock pulse φ after the input IN goes low.

When the input IN is at a high level, point A is always at a high level, and when the clock pulse φ is at a high level, transistors 42 and 41 are both turned off and point A becomes a high impedance state. When the clock pulse φ is at a low level, the transistor 42 becomes conductive, so that point A becomes a low impedance state. Further, when the clock pulse φ is at a high level, the transistor 43 is turned on and the output OUT becomes a low impedance and low level state. When clock pulse φ is low level, transistor 4
3 is turned off and transistors 44 and 4
Since 5 is also off, the output OUT enters a high impedance state and maintains the previous level. Therefore, if the input signal IN changes from a low level to a high level while the clock pulse φ is at a low level, the output signal OUT changes from a high impedance high level state to a low impedance low level state at the rise of the clock pulse φ. Changes to As is clear from the above, the circuit shown in Figure 4a is
As shown in FIG. 5, when the input signal IN rises or falls during the low level period of the clock pulse φ, it operates as a shift circuit that generates a falling or rising output OUT at the rising edge of the clock pulse φ.

FIG. 6 shows a CMIS according to another embodiment of the present invention.
A shift circuit is shown. In the circuit shown in FIG. 4, the source of the transistor 41 in the circuit shown in FIG.

The circuit shown in FIG. 6 performs the same shift operation as the circuit shown in FIG. 4a, but differs from the circuit shown in FIG. 4a in that the input signal is output without being inverted.

FIG. 7a shows a shift circuit according to yet another embodiment of the invention. The circuit in the figure includes an initial stage CMIS consisting of an N-channel transistor 71 and a P-channel transistor 72, N-channel transistors 73 and 74, and a P-channel transistor 75.
The next stage CMIS circuit consisting of N channel transistors 76, 77 and P channel transistor 7
8 and 79 are connected in series between the ground and the power supply _Vcc . The first stage and each second stage have the same configuration as the circuit shown in FIG. 4a. The signal from the output point A of the first stage circuit is applied to the gate of the transistor 76 of the third or final stage CMIS circuit, and the transistors 77 and 7
The output point B of the next stage circuit is connected to the gate of 8,
A clock pulse φ is applied to the gate of transistor 79.

FIG. 7b shows an equivalent circuit of the circuit shown in FIG. 7a. In other words, this equivalent circuit is the inverter 81
, a transfer gate consisting of transistors 82 and 83, an inverter 84, and a transfer gate consisting of transistors 85 and 86 are connected in cascade. driven.

The operation of the circuit shown in FIG. 7a will be explained with reference to FIG. When the input signal IN is at a low level, an inverted signal of the clock pulse φ is generated at point A. When the clock pulse φ is at a high level, point A is at a low level and transistor 73 is turned on, so that the next stage CMIS circuit is connected to transistors 74 and 75.
The CMIS inverter circuit consists of the following, and point B is in a low impedance and high level state. When clock pulse φ is at a low level, transistor 7
3 is cut off, and since point A is at a high level, transistors 74 and 75 are also cut off, and point B becomes a high impedance state, maintaining the previous level. When the clock pulse φ is at a high level, the final stage output OUT is output from the transistor 79.
is off, point B is at a high level, so transistor 78 is also off, and point A is at a low level, so transistor 76 is also off, causing the output
OUT goes into a high impedance state and maintains the previous voltage level. Furthermore, when the clock pulse φ becomes a low level, the transistor 79 is turned on and the point A becomes a high level, so the transistor 76 is also turned on, and since the point B is a high level, the output OUT is in a low impedance and low level state. Become. Therefore, as is clear from FIG. 8, when the input signal IN changes from a high level to a low level, the output OUT falls at the first fall of the clock pulse after this change.

Next, when the input signal IN is at a high level, when the clock pulse φ is at a high level, point A becomes a high impedance high level and point B becomes a low impedance low level. In this case, since the transistor 79 is off and the transistor 77 is also off, the output OUT enters a high impedance state and maintains the previous level. Therefore, when input IN rises from low level to high level, output OUT
rises from a low level to a high level at the first rising edge of the clock pulse φ after the rising edge of the input IN, as shown in FIG. As is clear from the above description, the circuit of FIG. 7a operates in the same manner as a so-called D-type flip-flop.

FIG. 9 shows still another embodiment of the present invention, in which the transistor 71 in the first stage circuit of the shift circuit shown in FIG.
N-channel transistor 91 and P
The input signal is supplied via a CMIS inverter made up of a channel transistor 92. This circuit is shown in Figure 7a at the point where the input signal is inverted and output to the output OUT.
Although the circuit is different from the one shown in FIG. 1, the basic shift operation is the same, so the explanation thereof will be omitted.

(7) Effects of the Invention As described above, according to the present invention, a dynamic shift circuit can be operated with a single clock, so that a so-called non-overlapping two-phase clock can be created. Since this is no longer necessary, the reliability of operation can be improved. Furthermore, by using a dynamic circuit, it is possible to significantly reduce the number of circuit elements and the area occupied by the circuit, compared to a static type circuit or a circuit using a single channel type MIS transistor.

[Brief explanation of drawings]

FIG. 1a is a block circuit diagram showing an example of a conventional dynamic shift circuit, and FIG. 1b is a block circuit diagram showing an example of a conventional dynamic shift circuit.
FIG. 2a is a block circuit diagram showing another example of a conventional dynamic shift circuit; FIG. 2b is a waveform diagram showing clock pulses used in the circuit shown in FIG. 2a. 3 is an electric circuit diagram showing a conventional clock gate circuit; FIG. 4a is an electric circuit diagram showing a dynamic shift circuit according to an embodiment of the present invention; FIG. 4b is an electric circuit diagram showing an equivalent circuit of the circuit shown in FIG. 4a, FIG. 5 is a waveform diagram for explaining the operation of the circuit shown in FIG. 4a, and FIG. FIG. 7a is an electric circuit diagram showing a dynamic shift circuit according to another embodiment of the invention;
is an electric circuit diagram showing a dynamic shift circuit according to yet another embodiment of the present invention, and FIG.
FIG. 8 is a waveform diagram for explaining the operation of the circuit shown in FIG. 7a, and FIG. 9 is a block circuit diagram showing an equivalent circuit of the circuit shown in FIG. FIG. 2 is an electrical circuit diagram showing a dynamic shift circuit according to an embodiment. 1, 4, 7, 10, 11, 41, 43, 44,
47, 61, 71, 73, 74, 76, 77, 8
2, 85, 91...N channel MIS transistor, 2, 5, 8, 12, 13, 42, 45, 4
8, 72, 75, 78, 79, 83, 86, 92
...P channel MIS transistor, 3, 6, 9,
46, 81, 84...Inverter.

Claims (1)

[Claims] 1. First and second P-channel MIS transistors whose sources are respectively connected to a first power supply, and a first P-channel MIS transistor whose gate and drain are commonly connected to the first P-channel MIS transistor. an N-channel MIS transistor and a second P-channel MIS transistor whose gate and drain are commonly connected to the second P-channel MIS transistor;
a third N-channel MIS transistor connected between the second N-channel MIS transistor and a second power supply, the drain of the first P-channel MIS transistor being connected to the second N-channel MIS transistor; 2, and applies a clock pulse to the gates of the first P-channel MIS transistor and the first and third N-channel MIS transistors, and inputs the source of the first N-channel MIS transistor. A dynamic shift circuit characterized in that a terminal and a drain of the second P-channel MIS transistor are used as output terminals. 2. Claim 1, wherein an N-channel MIS transistor is connected between the source electrode of the first N-channel MIS transistor and the second power supply, and an input signal is applied to the gate of the N-channel MIS transistor. Dynamic shift circuit described in . 3. The dynamic shift circuit according to claim 1, wherein the input signal is input to the source of the first N-channel MIS transistor via another inverter.