JPH0376559B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a dynamic shift circuit, and more particularly to a dynamic shift circuit constructed of a CMIS circuit and operable by a single clock pulse.

(2) Background of the technology In recent years, the number of LSI circuits such as semiconductor memories or microcomputers that use the CMIS process to save power has increased. However, the CMIS circuit is N-MIS or P-
Compared to single-channel circuits such as MIS, it requires about twice or three times the number of elements or circuit area, and as a result, the overall size of the chip tends to increase. In order to miniaturize the CMIS circuit, it is effective to make the internal circuit a dynamic circuit, especially in recent LSIs such as microcomputers.
It is necessary to make effective use of the fact that its internal circuit is composed of synchronous circuits.

(3) Prior art and problems Figure 1a shows a conventional transfer gate constructed using the CMIS process. This circuit includes a circuit in which an N-channel MIS transistor 1 and a P-channel MIS transistor 2 are connected in parallel and are turned on and off by clocks φ and of mutually opposite phases shown in FIG. 1a, and an inverter 3 that operates as a buffer amplifier. . The input signal IN is outputted via the transistors 1 and 2 and the inverter 3, which are turned on by the clock signals φ and, respectively, and an output signal OUT synchronized with the clock signals φ and is obtained.

FIG. 2a shows a conventional shift circuit constructed by cascading two of the above-mentioned transfer gates and used to construct a circuit such as a shift register or a counter. The circuit in the figure consists of a first-stage transfer gate composed of an N-channel MIS transistor 4, a P-channel MIS transistor 5, and an inverter 6;
It includes a next-stage transfer gate constituted by an MIS transistor 7, a P-channel MIS transistor 8, and an inverter 9. Each of the transistors 4 and 5 of the first stage transfer gate receives clocks φA and _A of opposite phase to each other as shown in FIG. 2b _.
The transistors 7 and 8 of the next stage transfer gate are respectively driven by clocks φ _{B and B} having mutually opposite phases shown in FIG. 2B. The clocks φ _B and _B are delayed from the clocks φ _A and φ _A by, for example, 1/2 period. Input signal used for first stage inverter
IN passes through transistors 4 and 5 controlled by clocks φ _A and _A and is stored in the stray capacitance present in the input circuit of inverter 6. The signal accumulated in the stray capacitance is input to the next stage transfer gate via the inverter 6, and the clock φ _B
The output signal OUT is taken out from the inverter 9 through the transfer gate at the timings B and _B.

FIG. 3 shows a circuit called a clock gate, which is constructed by connecting two N-channel MIS transistors 10, 11 and two P-channel MIS transistors 12, 13 in series between the power supply Vcc and the ground. Ru. The input signal IN is applied to the gates of transistors 11 and 12, and the output signal OUT is applied to the gates of transistors 11 and 12.
2 common drain. The gates of transistors 10 and 13 are shown in FIG. 1b, respectively.
The clocks φ and having mutually opposite phases shown in are applied. In the circuit of FIG. 3, when the clock φ is at a high level and the clock is at a low level, transistors 10 and 13 are both turned on.
Input signal IN is inverted and output as output signal OUT.

A disadvantage of each of the conventional circuits described above is that they require two types of clocks that are opposite in phase or complementary to each other. Furthermore, when constructing a circuit such as a shift register or a counter using the above-mentioned transfer gate or clock gate, two sets of clocks having mutually opposite phases as shown in FIG. 2b are used, resulting in a total of four types of clock signals. I need. Furthermore, it is necessary that the clocks having opposite phases to each other are so-called non-overlapping clocks, and therefore it is necessary that the clocks having opposite phases to each other do not both go to a high level or a low level at the same time. However, with non-overlapping clocks, the higher the clock frequency and the higher the duty cycle of the clock is 50
%, the more susceptible it is to circuit delays and the more difficult it becomes to create.

(4) Purpose of the Invention In view of the problems with the conventional type described above, the purpose of the present invention is to reduce the number of types of clocks required in a CMIS-type dynamic shift circuit by operating the shift circuit with a single clock. The objective is to improve the reliability of operation.

(5) Structure of the invention According to the present invention, the first and second PPSs whose sources are respectively connected to the first power source
a first N-channel MIS transistor whose gate and drain are commonly connected to the first P-channel MIS transistor; a second P-channel MIS transistor and a second N-channel MIS transistor;
and a second and third N-channel MIS transistor connected in series between the power supplies of the first P-channel MIS transistor and the second P-channel MIS transistor.
A clock pulse is input to the gate of the first P-channel MIS transistor and the first and second N-channel MIS transistors, and the gate of the third N-channel MIS transistor is connected to the gate of the third N-channel MIS transistor. By providing a dynamic shift circuit, the dynamic shift circuit is connected to the source of a first N-channel MIS transistor, which serves as an input terminal, and the drain of the second P-channel MIS transistor serves as an output terminal. achieved.

(6) Examples of the invention Examples of the invention will be described below with reference to the drawings. FIG. 4a shows a dynamic shift circuit according to one embodiment of the present invention. The circuit in the figure includes a first-stage CMIS circuit consisting of an N-channel MIS transistor 41 and a P-channel MIS transistor 42 connected in series, an N-channel CMIS transistor 43 connected in series between a power supply Vcc and ground,
44 and a next-stage CMIS circuit consisting of a P-channel MIS transistor 45, etc. The source of the transistor 42 is connected to the power supply Vcc, and the source of the transistor 41 is applied with the input signal IN.
Also, the clock pulse φ is the transistor 42, 4
1 and 44 gates. The drains of transistors 42 and 41 are commonly connected to each other in the first stage.
Taken out as output A of the CMIS circuit and sent to the next stage
It is input to the gate of transistor 45 of the CMIS circuit. The output OUT of the next stage CMIS circuit is taken out from the commonly connected drains of transistors 44 and 45.

FIG. 4b shows the circuit shown in FIG.
An equivalent circuit using a phase clock is shown. That is, the equivalent circuit in the figure is the inverter 46
It is constituted by a parallel circuit of an N-channel MIS transistor 47 and a P-channel MIS transistor 48, which are driven by a two-phase clock φ and a two-phase clock φ and 48, respectively.

Next, the operation of the circuit shown in FIG. 4a will be explained using FIG. If input IN is low level, first stage
The CMIS circuit becomes equivalent to the CMIS inverter and reaches point A.
A signal obtained by inverting the clock pulse φ is output. In this case, the transistor 43 of the next stage CMIS circuit is off, and since the level at point A is low during the period when the clock pulse φ is at a high level, the transistor 45 is turned on and the output OUT becomes a low impedance high level. clock pulse φ
During the low level period, the level at point A becomes high level, so the transistor 45 is also turned off, and the output OUT becomes a high impedance state, that is, a floating state, as shown by the signal Z in FIG. is retained as is. Therefore, the output OUT is the input IN
After the clock pulse φ becomes low level, it remains high level from the first rising edge of the clock pulse φ.

When the input IN is at a high level, point A is always at a high level, and when the clock pulse φ is at a high level, transistors 42 and 41 are both turned off and point A becomes a high impedance state. When the clock pulse φ is at a low level, the transistor 42 becomes conductive, so that point A becomes a low impedance state. Further, when the clock pulse φ is at a high level, the transistor 44 is turned on and the transistor 43 is turned on, so that the output OUT has a low impedance and a low level. When the clock pulse φ is at a low level, the transistor 44 is turned off, and since the transistors 44 and 45 are also turned off, the output OUT enters a high impedance state and maintains the previous level. Therefore, while the clock pulse φ is at a low level, the input signal
When IN changes from a low level to a high level, the output signal OUT changes from a high impedance high level state to a low impedance low level state at the rising edge of the clock pulse φ. As is clear from the above, in the circuit shown in FIG. 4a, the input signal IN is clock pulse φ, as shown in FIG.
When the clock pulse φ rises or falls during the low level period, it operates as a shift circuit that generates an output OUT that falls or rises at the rising edge of the clock pulse φ.

FIG. 6 shows a CMIS according to another embodiment of the present invention.
A shift circuit is shown. In the circuit shown in the figure, the source of the transistor 41, that is, the input signal terminal, in the circuit shown in FIG.

The circuit shown in FIG. 6 performs the same shift operation as the circuit shown in FIG. 4a, but differs from the circuit shown in FIG. 4a in that the input signal is output without being inverted.

FIG. 7a shows a shift circuit according to yet another embodiment of the invention. The circuit shown in the figure includes a first-stage CMIS circuit consisting of an N-channel transistor 71 and a P-channel transistor 72, a first-stage CMIS circuit consisting of N-channel transistors 73, 74, and a P-channel transistor 75, an N-channel transistor 76, 77, a P-channel transistor 78, A third stage CMIS circuit 79 is connected in series between the ground and the power supply Vcc. The first stage and next stage circuits have the same configuration as the circuit shown in FIG. 4a. The third or final stage
A signal from output point A of the first stage circuit is applied to the gates of the CMIS circuit and transistor 76, and a signal from output point B of the next stage circuit is applied to the gates of transistors 77 and 78.
is connected, and a clock pulse φ is applied to the gate of transistor 79.

FIG. 7b shows an equivalent circuit of the circuit shown in FIG. 7a. In other words, this equivalent circuit is the inverter 81
, a transfer gate consisting of transistors 82 and 83, an inverter 84, and a transfer gate consisting of transistors 85 and 86 are connected in cascade. driven.

The operation of the circuit shown in FIG. 7a will be explained with reference to FIG. When the input signal IN is at a low level, an inverted signal of the clock pulse φ is generated at point A. Then, when the clock pulse φ is at a high level, point A becomes a low level, and since the transistor 75 is turned on, the low impedance at point B becomes a high level state. When clock pulse φ is at a low level, transistor 74 is cut off, and since point A is at a high level, transistors 74 and 75 are also cut off and point B becomes a high impedance state, maintaining the previous level. Final stage output OUT
When the clock pulse φ is at a high level, the transistor 79 is on, and since the point B is at a high level, the transistor 78 is also off, and since the point A is at a low level, the transistor 76 is also off, and the output OUT is a high impedance. state and maintains the previous voltage level. Also, when the clock pulse φ becomes low level, the transistor 7
Since the ON point A of 9 is at a high level, the transistor 76 is also turned on, and since the point B is at a high level, the output OUT is in a low impedance and low level state. Therefore, as is clear from FIG. 8, when the input signal IN changes from a high level to a low level, the output OUT falls at the first fall of the clock pulse after this change.

Next, when the input signal IN is at a high level, when the clock pulse φ is at a high level, point A becomes a high impedance high level and point B becomes a low impedance low level. In this case, since the transistor 79 is off and the transistor 77 is also off, the output OUT enters a high impedance state and maintains the previous level. Therefore, when input IN rises from low level to high level, output OUT
rises from a low level to a high level at the first rising edge of the clock pulse φ after the rising edge of the input IN, as shown in FIG. As is clear from the above description, the circuit of FIG. 7a operates in the same manner as a so-called D-type flip-flop.

FIG. 9 shows still another embodiment of the present invention, in which the transistor 71 in the first stage circuit of the shift circuit shown in FIG.
An input signal is supplied to the source of the CMIS inverter including an N-channel transistor 91 and a P-channel transistor 92. This circuit has a seventh point in that the input signal is inverted and output to the output OUT.
Although the circuit is different from the circuit shown in FIG. a, the basic shift operation is the same, so a description thereof will be omitted.

(7) Effects of the Invention As described above, according to the present invention, since the dynamic shift circuit can be operated with a single clock, there is no need to create a so-called non-overlap type two-phase clock. Therefore, the reliability of operation can be improved. Furthermore, by using a dynamic circuit, it is possible to significantly reduce the number of circuit elements and the area occupied by the circuit, compared to a static type circuit or a circuit using a single channel type MIS transistor.

[Brief explanation of drawings]

FIG. 1a is a block circuit diagram showing an example of a conventional dynamic shift circuit, and FIG. 1b is a block circuit diagram showing an example of a conventional dynamic shift circuit.
FIG. 2a is a block circuit diagram showing another example of a conventional dynamic shift circuit; FIG. 2b is a waveform diagram showing clock pulses used in the circuit shown in FIG. 2a. 3 is an electric circuit diagram showing a conventional clock gate circuit; FIG. 4a is an electric circuit diagram showing a dynamic shift circuit according to an embodiment of the present invention; FIG. 4b is an electric circuit diagram showing an equivalent circuit of the circuit shown in FIG. 4a, FIG. 5 is a waveform diagram for explaining the operation of the circuit shown in FIG. 4a, and FIG. FIG. 7a is an electric circuit diagram showing a dynamic shift circuit according to another embodiment of the invention;
is an electric circuit diagram showing a dynamic shift circuit according to yet another embodiment of the present invention, and FIG.
FIG. 8 is a waveform diagram for explaining the operation of the circuit shown in FIG. 7a, and FIG. 9 is a block circuit diagram showing an equivalent circuit of the circuit shown in FIG. FIG. 2 is an electrical circuit diagram showing a dynamic shift circuit according to an embodiment. 1, 4, 7, 10, 11, 41, 43, 44,
47, 61, 71, 73, 74, 76, 77, 8
2, 85, 91...N channel MIS transistor, 2, 5, 8, 12, 13, 42, 45, 4
8, 72, 75, 78, 79, 83, 86, 92
...P channel MIS transistor, 3,6,
9, 46, 81, 84...inverter.

Claims (1)

[Claims] 1. First and second P-channel MIS transistors whose sources are respectively connected to a first power supply, and a first P-channel MIS transistor whose gate and drain are commonly connected to the first P-channel MIS transistor. The first P-channel MIS transistor includes an N-channel MIS transistor, and second and third N-channel MIS transistors connected in series between the second P-channel MIS transistor and a second power supply. The drain is connected to the gate of the second P-channel MIS transistor, and the clock pulse is connected to the gate of the second P-channel MIS transistor.
MIS transistor and the first and second N channels
the gate of the third N-channel MIS transistor is connected to the source of the first N-channel MIS transistor, which is used as an input terminal;
A dynamic shift circuit characterized by using the drain of the MIS transistor as the output terminal. 2. The dynamic device according to claim 1, wherein an N-channel MIS transistor is connected between the source of the first N-channel MIS transistor and the second power supply, and a signal is input to the gate of the transistor. shift circuit. 3. The input signal is passed through another inverter to the first
The dynamic shift circuit according to claim 1, wherein the dynamic shift circuit is configured to input to the source of an N-channel MIS transistor.