JPS636897Y2

JPS636897Y2 -

Info

Publication number: JPS636897Y2
Application number: JP2171281U
Authority: JP
Priority date: 1981-02-18
Filing date: 1981-02-18
Publication date: 1988-02-27
Also published as: JPS57135134U

Description

【考案の詳細な説明】本考案はクロツクによりスイツチング制御され
るCMOSインバータを用いた分周回路に関する
ものである。[Detailed Description of the Invention] The present invention relates to a frequency dividing circuit using a CMOS inverter that is switching controlled by a clock.

従来の分周回路の例を第１図に示す。第１図の
分周回路の動作は周知であり、詳しい動作の説明
はしない。端子３及び４に入力されるクロツク信
号Ｃ＝「高」及び＝「低」でトランジスタ（以
下、Trという）５，６，１１及び１２が「オン」
し、他のTrは「オフ」であり、端子１９及び２
０から出力Ｑ及びをインバータ（以下、Tvと
いう）１７と１８でラツチし出力する。また、
Tv１３と１４によつて信号＝Ｑと信号Ｍ＝
である。 An example of a conventional frequency dividing circuit is shown in FIG. The operation of the frequency divider circuit shown in FIG. 1 is well known and will not be described in detail. When the clock signal C input to terminals 3 and 4 is "high" and "low", transistors (hereinafter referred to as Tr) 5, 6, 11 and 12 are "on".
However, the other transistors are "off" and terminals 19 and 2
0 to output Q and are latched by inverters (hereinafter referred to as Tv) 17 and 18 and output. Also,
Signal = Q and signal M = by Tv13 and 14
It is.

次に信号Ｃ＝「低」及び＝「高」でTr……７，
８，９及び１０が「オン」と、他のTrは「オフ」
するとIv１４と１５で信号とＭをラツチしIv１
６と１７を通して出力Ｑとがそれぞれ反転す
る。 Next, with signal C = “low” and = “high”, Tr……7,
8, 9 and 10 are "on" and other Tr are "off"
Then, the signal and M are latched at Iv14 and 15, and Iv1
6 and 17, the output Q is inverted, respectively.

しかし、従来の分周回路は素子数（Trの数）
が20個と多い。 However, in conventional frequency divider circuits, the number of elements (number of Tr)
There are as many as 20 pieces.

本考案の目的は、分周回路の素子数を従来のも
のよりも少なくするにある。 An object of the present invention is to reduce the number of elements in a frequency dividing circuit compared to conventional circuits.

本考案による分周回路を一実施例について図面
を参照して説明する。 An embodiment of the frequency dividing circuit according to the present invention will be described with reference to the drawings.

第２図は本考案による回路図であり、１と２は
それぞれV_DD＝０とV_SS＜０の電源端子、３と４
は互いに逆位相のクロツク信号Ｃとの信号入力
端子、２１と２２はスイツチング回路、１３〜１
８はCMOSのインバータ（以下、Ivという）、１
９と２０は出力端子で、Iv１３と１８はスイツチ
ング回路２１にIv１５と１６はスイツチング回路
２２にそれぞれ制御され、スイツチング回路２１
は信号Ｃ＝「高」でＮチヤネルTr（以下、Ｎ
Tr）２１２と信号は「低」でＰチヤネルTr
（以下、Ｐ Tr）２１１がともに「オン」し、ス
イツチング回路２２は信号Ｃは「低」でＰ Tr
２２１と信号は「高」でＮ Tr２２２がとも
に「オン」し、Ｍとは信号である。 Figure 2 is a circuit diagram according to the present invention, 1 and 2 are power supply terminals with V _DD = 0 and V _SS < 0, respectively, 3 and 4
are signal input terminals for clock signals C having mutually opposite phases, 21 and 22 are switching circuits, 13 to 1
8 is a CMOS inverter (hereinafter referred to as Iv), 1
9 and 20 are output terminals, Iv13 and 18 are controlled by the switching circuit 21, Iv15 and 16 are controlled by the switching circuit 22, and the switching circuit 21
is N channel Tr (hereinafter, N
Tr) 212 and signal is "low" and P channel Tr
(hereinafter referred to as P Tr) 211 are both "on", and the switching circuit 22 has a signal C "low" and P Tr
221 and the signal are "high" and both NTr222 are "on", and M is the signal.

第３図は第２図の動作を示したタイミング図で
ある。 FIG. 3 is a timing diagram showing the operation of FIG. 2.

次に動作について説明する。信号Ｃを「高」、
信号を「低」とすると回路２１が「オン」しIv
１３と１８がインバータとして機能する。ここで
出力Ｑは「高」、出力は「低」であるとすると
Iv１７と１８で出力Ｑとをラツチしている。 Next, the operation will be explained. Set signal C to "high",
When the signal is set to "low", circuit 21 turns "on" and Iv
13 and 18 function as inverters. Here, if the output Q is "high" and the output is "low"
The output Q is latched at Iv17 and 18.

またIv１３と１４により信号＝Ｑ＝「高」と
信号Ｍ＝＝「低」となる。この時、スイツチン
グ回路２２は「オフ」状態であるためIv１５と１
６はインバータとして機能せず出力はフローテイ
ング状態になつている。次に信号Ｃ＝「低」、信号
Ｃ＝「高」となるとスイツチング回路２２が「オ
ン」しIv１５と１６はインバータとして機能す
る。この時スイツチング回路２１は「オフ」とな
るのでIv１３と１８はインバータとしての機能を
失う。よつてIv１４と１５により信号とＭがラ
ツチされ、Iv１６と１７により新たに反転した出
力Ｑ＝「低」と出力＝「高」を出力する。 Also, signal Q becomes "high" and signal M becomes "low" due to Iv13 and 14. At this time, since the switching circuit 22 is in the "off" state, Iv15 and 1
Iv13 and 18 do not function as inverters and the output is floating. Next, when signal C="low" and signal C="high", switching circuit 22 turns "on" and Iv15 and 16 function as inverters. At this time, switching circuit 21 turns "off", so Iv13 and 18 lose their function as inverters. Therefore, Iv14 and 15 latch the signal and M, and Iv16 and 17 output the newly inverted output Q="low" and output="high".

続いて信号Ｃ＝「高」、信号＝「低」となると
スイツチング回路２１が「オン」し、スイツチン
グ回路２２が「オフ」してIv１３と１８が再びイ
ンバータとして機能し、Iv１５と１６がその機能
を失い、Iv１７と１８により、そのまま出力をラ
ツチし、出力Ｑ＝「低」と出力＝「高」である。 Subsequently, when the signal C becomes "high" and the signal becomes "low," the switching circuit 21 turns "on," the switching circuit 22 turns "off," and Iv13 and 18 function as inverters again, and Iv15 and 16 function as inverters. The output is latched as is by Iv17 and 18, and the output Q is "low" and the output is "high."

以上から、信号Ｃの「高」から「低」の変化
（信号の「低」から「高」の変化）で出力Ｑと
Ｑは、信号Ｃ及びの変化の前後で出力状態を反
転させ、信号Ｃの「低」から「高」（信号の
「高」から「低」）の変化で出力Ｑとは、信号Ｃ
及びの前後で出力状態をラツチし不変である。 From the above, when signal C changes from "high" to "low" (signal changes from "low" to "high"), outputs Q and Q reverse their output states before and after the change in signal C and The output Q is the change in signal C from "low" to "high" (from "high" to "low" of the signal).
The output state is latched before and after and remains unchanged.

以上の動作は第３図に示した通りである。 The above operation is as shown in FIG.

本考案による分周回路は、素子（トランジス
タ）の数にして16個で良く、第２図のスイツチン
グ回路２１のＰ Tr２１１と、Ｎ Tr２１２の
制御能力はIv１３もしくはIv１８の一つのインバ
ータの制御だけでよい。すなわち、Iv１３と１８
のそれぞれの出力＝Ｑと出力となるからであ
る。 The frequency dividing circuit according to the present invention only requires 16 elements (transistors), and the control ability of PTr211 and NTr212 of the switching circuit 21 in FIG. good. i.e. Iv13 and 18
This is because each output = Q and output.

以上の如く、分周回路を構成するので次の効果
を有する。 Since the frequency dividing circuit is configured as described above, it has the following effects.

数字数が16個なので、従来のものより素子数
が４個少ない。 Since there are 16 numbers, the number of elements is 4 fewer than the conventional one.

２つのスイツチング回路は、それぞれ２つの
インバータを制御しているが、スイツチング回
路のうちの１つは、１つのインバータ分の制御
能力でよい。 The two switching circuits each control two inverters, but one of the switching circuits may have the control capability of one inverter.

より少ない素子数とそれにともなつてのより
少ない配線数とによつて、より少ない面積で半
導体上に分周回路を構成できる。 With a smaller number of elements and a correspondingly smaller number of wires, a frequency dividing circuit can be constructed on a semiconductor with a smaller area.

集積回路の歩留が向上する。 The yield of integrated circuits is improved.

[Brief explanation of the drawing]

第１図は従来例の分周回路の回路図、第２図は
本考案による分周回路の回路図、第３図は第２図
の分周回路の動作を示したタイミング図である。１……V_DD電源端子、２……V_SS電源端子、３
と４……信号入力端子、１３〜１８……CMOS
インバータ、１９と２０……出力端子、２１と２
２……スイツチング回路、Ｃ，……クロツク信
号、Ｑ，……出力、Ｍ，……信号。 FIG. 1 is a circuit diagram of a conventional frequency dividing circuit, FIG. 2 is a circuit diagram of a frequency dividing circuit according to the present invention, and FIG. 3 is a timing diagram showing the operation of the frequency dividing circuit of FIG. 1...V _DD power supply terminal, 2...V _SS power supply terminal, 3
and 4...signal input terminal, 13-18...CMOS
Inverter, 19 and 20...Output terminal, 21 and 2
2...Switching circuit, C,...clock signal, Q,...output, M,...signal.

Claims

[Scope of utility model registration request]

In a semiconductor circuit using an insulated gate field emission transistor, an N-channel transistor is controlled by a first clock, and a P-channel transistor is controlled by a second clock having an opposite phase to the first clock.
a first switching circuit comprising a channel transistor; a P-channel transistor different from the first switching circuit controlled by the first clock; and the first switching circuit controlled by the second clock. a second switching circuit comprising another N-channel transistor, a first inverter controlled by the first switching circuit, a second inverter receiving the output of the first inverter, and the second switching circuit. a third inverter that is controlled by the second switching circuit and receives the output of the second inverter and outputs the output to the input of the second inverter; a fourth inverter that is controlled by the second switching circuit and receives the output of the second inverter; , a fifth inverter receiving the output of the fourth inverter; a fifth inverter controlled by the first switching circuit;
a sixth inverter receiving the output of the inverter and outputting it to the input of the fifth inverter and the first inverter;
A frequency divider circuit consisting of an inverter.