JPH0349413A - Cmos latch circuit with set - Google Patents

Abstract

PURPOSE:To decrease the number of circuit elements by three elements and to simplify a wiring pattern by using an inverter and 9 MOS transistors. CONSTITUTION:A CMOS latch circuit is composed of an inverter 1, first conductive type 1 st and 2nd MOS transistors Q1 and Q2, second conductive type 3rd-5th MOS transistors Q3-Q5, first conductive type 6th MOS transistor Q6, first conductive type 7th and 8th MOS transistors Q7 and Q8 and second conductive type MOS transistor Q9. Thus, an area to be occupied by the element and wiring pattern is reduced and a chip size can be made compact.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a CMOS latch circuit, and particularly to a CMOS latch circuit with a set.
Regarding MOS latch circuits.

[Prior Art] Conventionally, this type of latch circuit has been configured as shown in FIG.

That is, between the second power supply VCC and the first power supply VS8, there is a P-channel MO8FETQ23. Q2° and N-channel MOS FET Q2□IQ20 are connected in series. Also, the second power supply ■. 0 and the drain of the P-channel MO8FETQ2□, the P-channel MO8FETQ23. A P-channel MOS FETQ27-Q2B is connected in series in parallel with Q2□. Furthermore, N-channel MOS F E
Between the drain of TQ2° and the first power supply VSS, the N-channel MO8FETQ23. In parallel with Q20 is an N-channel MOS FETQ215. Q24 is connected in series.

A data input signal is input to each gate of MO8FETQzo and Q23. Also, MO8FE TQ
21. A first gate input signal G is input to each gate of Q2G. Furthermore, MO8FETQ2゜, Q2
A second gate input signal G is input to each gate of 5.

On the other hand, the commonly connected MO5FETQ21. Q2゜.

The drains of Q2 and Q26 are connected to one input terminal of the NAND gate 2. Further, a set input signal is input to the other input terminal of this NAND gate 2. The output signal of this NAND gate 2 is output as the data output signal Q, and the MO8FET
Q24. It is supplied to each gate of Q2□ and the input terminal of the inverter 3.

The output of the inverter 3 is output as a data output signal Q.

Next, the operation of the CMOS latch circuit configured as described above will be explained.

Now, when the first gate input signal G is "H" and the second gate input signal G is "+1,1", when the data input signal R is taken in, the data input signal R is the first stage. CM
The signals are inverted by the OS inverter, then returned to the same phase through the NAND gate 2, and output as the data output signal Q.

Next, when the first gate input signal G changes to “L°” and the second gate input signal G changes to “H”, MO8FETQ21
Both S and Q2e turn on, MO5FETQ 241 Q
27 receives the data output signal Q via the NAND gate 2.
Since the signal Q is given positive feedback, the data output signal Q is held as it is.

When the first gate input signal G is "L°" and the second gate input signal °d- is "H", the set input signal S is "L"
Then, the output of the NAND gate 2, that is, the data output signal Q becomes "H11".

Even in this case, MO8FETQ24. NAN for Q27
Since positive feedback is applied via the D gate 2, the data output signal Q is held at "H''.

[Problems to be Solved by the Invention] In the conventional CMOS latch circuit described above, the NAND gate 2 consists of four elements and the inverter 3 consists of two elements, so a total of 14 elements are required. There is a problem in that when a large number of devices are integrated, the chip size increases.

Furthermore, in the conventional CMOS latch circuit, the wiring for the first gate input signal is connected to the gates of the N-channel MO8FETQ21 and the P-channel MO8FETQ28, and the wiring for the second gate input signal is connected to the N-channel MO8FETQ28.
Q215 and the gate of P-channel MO8FET Q2°. Therefore, as shown in FIG. 7, it is necessary to wire the first and second gate input signals to the P-channel MO9 region and the N-channel MO9 region on the chip, respectively, and the area occupied by the wiring pattern is increases, which also causes the problem of an increase in chip size.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a CMOS latch circuit with a set, which can reduce the number of elements and the area occupied by wiring patterns, thereby reducing the chip size.

[Means for Solving the Problems] A CMOS latch circuit with a set according to the present invention includes an inverter connected between an inverted data output terminal and a data output terminal, and an inverted data output terminal and a first power supply terminal. first and second MOS transistors of a first conductivity type which are connected in series between and input a first gate input signal and a data input signal to their gates, respectively, a second power supply terminal and the inverted data output terminal; third, fourth, and fifth MOS transistors of a second conductivity type connected in series between the transistors and having gates input with a set input signal, a data input signal, and a second gate input signal, respectively; a sixth MOS transistor of the first conductivity type connected between the data output terminal and the first power supply terminal and inputting a reset input signal to its gate; and the inverted data output terminal and the first power supply terminal. seventh and eighth MOS) transistors of a first conductivity type connected in series between the second power supply terminal and the second power supply terminal; a ninth MOS of a second conductivity type connected between the inverted data output terminal and inputting the output signal of the inverter to its gate;
It is characterized by being equipped with a transistor.

[When the third MOS transistor driven by the action coset input signal is in the on state, and the first and fifth MOS transistors are turned on by the first and second gate input signals, the first stage CMOS inverter functions. The data input signal is then captured and inverted. Furthermore, the output is returned to the same phase by an inverter and output as a data output signal.

When the first and fifth MOS transistors are turned off by the first and second gate input signals, the seventh MOS transistor is turned off.
S) The transistor is turned on and the 8th and 9th MO
S) Positive feedback of the data output signal to the gate of the transistor causes the data output signal to be held.

On the other hand, when the sixth MOS transistor is turned on by the set input signal, the inverted data output terminal is forcibly set to the first power supply level, and the data output terminal is forcibly set to the second power supply level.

As described above, according to the present invention, the number of circuit elements can be reduced by three elements compared to the conventional circuit, and the number of gate input signal wirings can be reduced to one each for the P-channel MOS region and the N-channel MOS region. It is better to set one each.

[Example] Hereinafter, an example of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing the configuration of a CMOS latch circuit with set priority set reset according to a first embodiment of the present invention.

Second power supply V. C and the first power supply Vss are P-channel MO8FETs QII, Q4, Q5 and N-channel MO8FETs Q1. Q2 is connected in series. Between the commonly connected drains of the M OS F E T Q s lQ a and the first power supply Vss, an N channel M OS F E T Q e and an N channel M
A series circuit of O8FETQ7-Qa is connected in parallel. Also, a second power source V. C and the MO8FETQI
, Q5, and the commonly connected drains thereof, a P-channel MO8FET Q9 is connected.

A data input signal is input to each gate of MO8FETQQ and Q4. The first gate input signal G is input to the gate of MO8FETQ. Also,
A second gate input signal G is input to each gate of MO8FETQ5 and Q7. Furthermore, MO8FETQ
A set input signal S is input to each gate of G and Qa.

On the other hand, the commonly connected MO8FETQ8. Qls.

Qol Q7. Each drain of Q9 is connected to the input terminal of inverter 1. The input signal to this inverter 1 is taken out as a data output signal Q. Further, the output signal of this inverter 1 is outputted as a data output signal Q, and is also supplied to each gate of MO8FETQθ+Qa.

Next, the CMOS according to this embodiment configured as described above
The operation of the latch circuit will be explained with reference to FIG.

First, it is assumed that the set input signal S is "L", the data input signal is "H1", and the data output signal Q is +1 Ll'. At this time, MO8FETQ2, Qa.

Q9 is on, MO8FETQ4. Qo and Qa are off.

Time 1. and the first gate input signal G is II H11 second
When the gate input signal G of MO8FET becomes “L”, the MO8FET
Since Qi = Qls is turned on, MO8FE T
Current flows through MO8FETQ11Q2 through Qe. Here, MO5FETQ1. If the total on-resistance value of Q2 is set to about 1/3 or less of the on-resistance of MO8FETQ, at time t2, the input of inverter 1 will be as shown in the input/output characteristic curve in Figure 3. , the output voltage becomes lower than the inverted input voltage ■1. Therefore, the data output signal Q output from inverter 1 is inverted and “H”.
MOS FETQe turns off.

As a result, the data output signal Q, which is the input of the inverter 1, is held at 0 [V], and the data output signal Q becomes V. 0
is maintained.

When the first gate input signal G becomes "L" and the second gate input signal G becomes "H" at time t3, MO8FETQ1
．． Q5 is off, MOS FET Q7 is on, but MOS FET Q a is on, MO8
Since F'ETQ9 remains off, data output signals Q and Q continue to be held at O[V] and Vcc, respectively.

Next, at time t4, the data input signal G becomes "L", and at time t5, the first gate input signal G becomes "H" again, and the second gate input signal G becomes "L".
When the gate input signal G of MOS F becomes “Lo”, MOS F
E T Q I, Q5 turns on, so MO8FET
Q4. Supply voltage v through Q5. o is applied to the input of inverter 1, the input potential of inverter 1 rises, and at time t8, inverter 91 (D output cover "L"!l
: Inverted, MO8FETQ9 is on, MO3FETQa
is turned off. This is it.

The data output signal Q, which is the input of inverter 1, is V.

The data output signal Q is held at 0 [V].

At time t7, when the first gate input signal G is IIL and the second gate input signal G is inverted to "H", the MOS F
E T Q 1. Q a is off, MO8FETQ7
turns on. At this time, since MO8FETQ9 is turned on, data output signal Q, which is the input of inverter 1, continues to hold O[V].

Furthermore, when the set input signal S becomes "H"' at time t8, MO8FETQa is turned off and MO8FETQ6 is turned on. At this time, MO8FETQ is on, so the on-resistance value of MO8FETQe is
If the on-resistance value of T Q e is set to approximately 1/3, at time t8, the input of the inverter 1 becomes lower than the input/output voltage V in FIG. 3, so the output data output from the inverter 1 Signal Q is inverted and becomes 11 HII, MO3FETQ8 is turned off and MO3FETQ8 is turned on. As a result, the data output signal Q, which is the input of the inverter 1, is held at 0[■], and the data output signal Q is held at Vcc.

Next, the layout of a chip using the CMOS latch circuit according to this embodiment, particularly the state of gate input wiring, will be explained with reference to FIG. In this embodiment, the wiring for the first gate input signal G is an N-channel MOS
Since it is input only to the gate of F E T Q l, P
It is not needed in the channel MO3 region. Further, the wiring for the second gate input signal G is a P-channel MOS F E
It is connected to T Q 5 and the gate of P-channel MO8FET Q7, so on the chip it is
One second gate input wiring is provided in the area, and N channel M
The connection to the O8 area can be made by appropriately extending it inside the chip.

FIG. 5 is a circuit diagram of a CMOS latch circuit according to a second embodiment of the present invention.

This embodiment differs from the first embodiment described above in the second power supply V. . MO8FETQ:+, Q4. Among Q5, MO8 is connected in series between the point where Q3 is placed on the input side of the inverter 1, and the input end of the inverter 1 and the first power supply VSg.
Of FETQ, Q2, Ql is placed on the first power supply VSS side, and the input terminal of inverter 1 is connected to inverter 4.
The point is that the data output signal Q is taken out through the .

Since the other configurations are similar to the circuit shown in FIG. 1, the same components as in FIG. 1 are given the same reference numerals and detailed explanations will be omitted.

The basic operation of this embodiment is the same as that of the first embodiment, and it is clear that the effects of the present invention can be achieved as in the previous embodiment.

In addition, the pulse width of the "H1 level" of the set signal S, the pulse width of the "H level" of the gate input signal G, and the pulse width of the "H level" of the gate input signal G.
After the pulse width of the "I" and "II" levels and the data input signal change, the gate input signal G changes from "H" to "L", and the gate input signal G changes from "'L" to "Ho". The data setting time is from each input to inverter 1.
is the time it takes for the change to occur. Therefore, when the fan-out of the inverter 1 is large, the load capacity becomes large and the switching time of the inverter 1 becomes long. however,
According to this embodiment, since the data output signal Q is taken out through two stages of inverters, the inverter 1 switches without being affected by the load of the data output signal Q at all. Therefore, even if the load of the data output signal Q is large, the "H" level pulse width of the set human input signal S, the "H" level pulse width of the gate input signal G, the "L" level pulse of the gate input signal G, This has the effect of shortening the width and the data setting signal of the data input signal.

In addition, a buffer formed by connecting two stages of inverters in series may be connected to the input of inverter 1 to output data output signal Q.
Alternatively, one inverter may be connected to the output of inverter 4 or inverter 1 to extract data output signal Q.

In addition, in the embodiment described above, MOSFETQ3
, Q4. Qa, Qe are P channel type, MOSFETQ
,,QQ,QG,Q7. Although Q8 has been described as an N-channel type, the former group may be an N-channel type, and the latter group may be a P-channel type. In this case, the MOS
Power supply voltage V is applied to inverter 1 via FETQ3, Q4゜Q6. When 0 is applied, MOSFET Q7 is turned off, so the elements of MOSFET Q3, Q4, and Q5 can be made smaller, and the input capacitance is also reduced.

[Effects of the Invention] As explained above, according to the present invention, the number of circuit elements can be reduced by three elements (20%) compared to the conventional one. In addition, the wiring of the gate input signal is also
There can be one each for the O8 region and the N-channel MO3 region, and the wiring pattern can be simplified. Therefore, the chip size can be reduced by about 30%.

Further, the present invention has the effect that a high-speed CMOS latch circuit can be provided by reducing the wiring capacitance of the gate input signal line.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a CMOS latch circuit according to the first embodiment of the present invention, Fig. 2 is a timing diagram showing the operation of the latch circuit, and Fig. 3 is a characteristic diagram showing the input/output characteristics of the latch circuit. , FIG. 4 is a plan view showing the wiring layout of the latch circuit, FIG. 5 is a circuit diagram of a CMOS latch circuit according to a second embodiment of the present invention, and FIG. 6 is a circuit diagram of a conventional CMOS latch circuit. FIG. 7 is a plan view showing the wiring layout of the latch circuit shown in FIG. 6. 1.3.4; Inverter, 2; NAND gate, Q
11 Q2z QG1 Q? l Qa+ Q201
Q2+1Q 24I Q2+I; N channel MO
8FET, Qa to Q51Q81Q2゜IQ23I Q
213I Q27; P-channel MO8FET 2; NAND gate 3; Inverter D; Data input signal G; First gate input signal G; Second gate input signal QQ; Data output signal S; Set input signal Vas; Power supply Vα; second power supply

Claims (1)

[Claims] (1) An inverter connected between an inverted data output terminal and a data output terminal, an inverter connected in series between the inverted data output terminal and a first power supply terminal, and a first gate input signal applied to each gate. and a first and second MOS transistor of a first conductivity type, which input a data input signal, are connected in series between a second power supply terminal and the inverted data output terminal, and have a set input signal and a data input signal at their gates, respectively. third, fourth, and fifth MOS transistors of a second conductivity type to which an input signal and a second gate input signal are input; and connected between the inverted data output terminal and the first power supply terminal; A sixth MOS transistor of a first conductivity type is connected in series between the inverted data output terminal and the first power supply terminal, and has a second gate input signal and a second gate input signal input to the gate, respectively. Seventh and eighth MOS transistors of a first conductivity type input the output signal of the inverter, and connected between the second power supply terminal and the inverted data output terminal, and have gates receiving the output signal of the inverter. A CMOS latch circuit with a set, comprising a ninth MOS transistor of a second conductivity type for input.