JPH0348932A - Memory access control method - Google Patents

Abstract

PURPOSE:To effectively utilize the function of a cache memory CM by executing a pre-read instruction to read the instruction or the data to access for the first time into the CM prior to the access. CONSTITUTION:When a mapped address serving as a pre-read instruction is sent to a pre-read controller 4 from a microprocessor 1, an address decoder 5 selects a chip and applies a selection signal (a) to the controller 4. A timing controller 6 of the controller 4 receives the signal (a) and starts a pre-read operation of a CM 3 to produce a timing signal (b). This signal (b) functions to hold an address to be pre-read and outputted to a data bus from the microprocessor 1 in an address register 7. The controller 6 produces a control signal (c) to the address which reads the instructions and the data out of a main memory 2. At the same time, the controller 6 produces a control signal (d) to write the instructions and data read out of the memory 2 into the CM 3 and reads them.

Description

Detailed Description of the Invention <Industrial Application Field> The present invention relates to a technology related to a cache memory used for speeding up access between a microprocessor and a main memory, and in particular the present invention relates to a memory access control method applied to control reading of instructions and data into a cache memory.

<Prior art> This type of memory system speeds up subsequent memory access by loading instructions and data in main memory into cache memory, which is faster than main memory, as needed, thereby increasing the execution speed of the microprocessor. It is intended to improve

By the way, if memory access is performed in the initial state where there are no instructions or data in the cache memory, a cache miss will occur and memory access between the microprocessor and main memory will take time, making it impossible to enjoy the effects of the cache memory. Cache memory is based on the probabilistic fact that instructions and data that have been read once are likely to be accessed again at some point in time, so even if a cache miss occurs, the instruction or data When the cache memory is used repeatedly, subsequent memory access becomes faster, and the effect of the cache memory becomes large.

<Problems to be Solved by the Invention> However, for example, in the case of data that is referenced only - degrees, it is not only wasteful to import the data from the main memory into the cache memory;
There is a problem in that the function of the cache memory is not effectively demonstrated, and the effects of using the cache memory cannot be enjoyed at all.

This invention was made with a focus on the above problem, and by adopting a method of loading instructions and data into the cache memory in advance before a cache miss occurs, the function of the cache memory is effectively utilized, thereby making it possible to access memory. The aim is to achieve faster speeds.

<Means for Solving the Problems> In order to achieve the above object, in the present invention, in a system using a cache memory for speeding up memory access, instructions and data to be accessed for the first time are A prefetch instruction for reading into the cache memory is executed in advance, and the data is read into the cache memory.

Effect> Since instructions and data to be accessed for the first time are read into the cache memory in advance before a cache miss occurs, the instructions and data are reliably cached when accessing the memory. Therefore, regardless of whether the instructions or data are used repeatedly, the function of the cache memory is effectively exhibited, and the effects of using the cache memory can always be enjoyed.

<Embodiment> FIG. 1 shows a schematic configuration of a memory system for implementing the present invention, in which a microprocessor 1. Main memory 2. In addition to the vertical structure such as the cache memory 3, a prefetch controller 4 is provided.

The microprocessor 1 accesses instructions and data from the main memory 4. In order to speed up this memory access, the microprocessor 1 transfers instructions and data from the main memory 4 to the main memory 2.
The data is imported into the cache memory 3, which is faster than the previous version.

This cache memory 3 has a smaller capacity than the main memory 2, but its memory access can be performed at high speed.

The prefetch controller 4 operates to read instructions and data in the main memory 2 to be accessed into the cache memory 3 in advance of the access based on a prefetch instruction as an I10 instruction given by the microprocessor 1. , as shown in FIG. 2, consists of a timing controller 6 and an address register 7.

In the case of this embodiment, prefetch control to the cache memory 3 is performed by setting the address of the main memory 2 to be prefetched in a register mapped to a fixed address of the microprocessor 1. The corresponding address is given to the main memory 2, and the instructions and data at the corresponding address in the main memory 2 are sent to the cache memory 3 and taken into the cache memory 3.

The read-ahead instruction is, for example, rMOV in assembler language.
Al, (AO) J. In the case of this prefetch instruction, the contents of register Al (address of main memory 2 to be prefetched) indicated by A1 inside microprocessor l are transferred to the register indicated by AO. It instructs to set it to the address indicated by the contents of.

When the mapped address is sent from the microprocessor l to the pre-read controller 4, the address decoder 5 selects a chip and provides a selection signal a to the pre-read controller 4.

The timing controller 6 of the look-ahead controller 4 is
When this selection signal a is received, a prefetch operation of the cache memory 3 is started, and a timing signal is sent to hold the address to be prefetched, which is output from the microprocessor l to the data bus, in the address register 7. occurs.

The timing controller 6 also generates a control signal C for the address at which instructions and data are to be read from the main memory I72, and a control signal for writing the instructions and data read from the main memory +72 into the cache memory 3. generate d.

FIG. 3 shows the timing of reading instructions and data by the microprocessor 1 when the instructions and data are accessed through the same bus.

Figure 3 (1) shows a conventional memory access control method in which a microprocessor sequentially reads instructions 0 to 9, and then a cache miss occurs when it reads data 0, which is accessed for the first time. There is. As a result, following this cache miss, 0 data is read from the main memory to the cache memory, and
This data will be taken into the microprocessor.

FIG. 3(2) shows a memory access control method according to the present invention, in which, before the microprocessor 1 accesses 00 data, it executes a prefetch instruction for 0 data and stores this data in the cache memory 3 in advance. Loading.

This data prefetching process is performed in parallel with reading other instructions, and after instructions 0 to 9 are read in sequence,
When 0 data is accessed to the memory, it is cached, thereby preventing time loss due to a cache miss.

<Effects of the Invention> As described above, the present invention executes a prefetch instruction to read an instruction or data to be accessed for the first time into the cache memory prior to the access. The purpose of the invention has been achieved, and the invention achieves remarkable effects, such as ensuring that data is cached when accessing the memory, the function of the cache memory being effectively exhibited at all times, and the effects of using the cache memory being enjoyed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a memory system for carrying out the present invention, FIG. 2 is a block diagram showing the configuration of a read-ahead controller, and FIG. 3 is an example of comparison between a conventional method and a method according to the present invention. FIG. l...Microprocessor 2...Main memory 3...Cache memory 4
・・・・Lookahead controller

Claims (1)

[Claims] In a system using a cache memory for speeding up memory access, a prefetch instruction is executed to read instructions and data to be accessed for the first time into the cache memory prior to the access. A memory access control method characterized by reading into a cache memory.