JPH0934785A - Prefetch controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a hit rate and to reduce memory capacitance in prefetch control. SOLUTION: On a main storage device 21, data to be processed are arranged for the unit of a page having prescribed data structure, and the processing object page is switched in every prescribed processing cycle. The page to be processed is designated to a page address register 24. At a page counter 25, the time during the page processing cycle period is counted and a count signal is sent out. According to this count signal, an offset address in the page to be processed and a register number (transfer destination) corresponding to this address are read out of a table 27. At a synchronous data transfer controller 28, the data to be processed are read out responding to the designated page and offset address and these data to be processed are prefetched into a register 26 designated at the transfer destination. Namely, the synchronous data transfer controller controls the transfer of data to be processed synchronously with the offset address and transfer destination according to the designated page.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a prefetch control device for prefetching data from a main storage device, and more particularly, to a prefetch control method for performing fixed data processing at high speed.

[0002]

2. Description of the Related Art In an information processing apparatus, a small-capacity, high-speed memory (a so-called cache memory) is arranged between a processor and a main storage device to shorten the access time from the processor to the main storage device. ing. That is, in a memory access (main memory access) executed on an information processing apparatus, generally, an accessed address has locality, and by using this property, frequently accessed data is stored in a cache memory. That is being done.

Referring to FIG. 2, when processor 11 accesses main storage device 12, word 1 accessed is accessed.
The contents of a continuous storage area (generally called a block) of a predetermined size including 3 are fetched from the main storage device 12 to the cache memory 14. As a result, most of the memory access (main memory access) can be achieved by accessing the cache memory 14 at high speed. That is, access to the low-speed main storage device can be reduced.

[0004]

As described above, in the conventional information processing apparatus, the data stored in the cache memory is determined depending on the so-called "locality" at the time of memory access. Some programs may not be as local as expected, and as a result, the prefetch hit rate may decrease.

Further, as described above, since the rough range is put together and the contents of the “data block that is likely to be accessed again in the near future” are fetched into the cache memory space, they are not used as a result. A storage space for fetching and storing data must be secured in the cache memory, and there is a problem that the use of the cache memory is not always efficient.

In particular, in the case where the data to be processed is arranged in the main memory in units of pages having a certain structure, the processing for each page data is routine, and the page to be processed is switched at a predetermined time period. However, the problem that the use of the cache memory is not efficient becomes more prominent.

An object of the present invention is to provide a prefetch control device in which the hit ratio does not decrease.

Another object of the present invention is to provide a prefetch control device that requires a small memory capacity.

[0009]

According to the present invention, the data to be processed is arranged between a main storage device storing the data to be processed on a page basis and a processor for processing the data to be processed, and the data to be processed is prefetched. A prefetch control device for storing the data to be processed as prefetch data, a table in which an address in the page and a transfer destination corresponding to the address in the page are defined, When specified, the data in the page to be processed is read as the data to be processed based on the address in the page in accordance with the page processing cycle, and the data to be processed is prefetched to the area in the storage device designated by the transfer destination A prefetch control device characterized by having control means for performing the prefetch control.

Here, the storage means is a plurality of registers, and each of the plurality of registers is used as an area of the storage means.

The prefetch control device further includes a page address register for designating a page to be processed, and a page counter for executing a count during the page processing period and transmitting a count signal representing the count number.
The in-page address and the transfer destination are read out from the table in synchronization with the count signal.

The control means may access the main storage device in accordance with the page to be processed and the address in the page to read the data in the page to be processed as the data to be processed. Transfer means for transferring the data to be processed to the designated prefetch register.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

Referring to FIG. 1, a data processing device to which the present invention is applied includes, for example, a main storage device 21 and a processor 22, and a prefetch control device 23 is provided between the main storage device 21 and the processor 22. Is arranged. The prefetch control device 23 includes a page address register (PAR) 24, a page counter (PCTR) 25, first to N-th (N is an integer of 2 or more) prefetch registers (PFR) 26, a time-source-destination table ( Time-Source-Destinat
ion Table: TSDT) 27 and a synchronous data transfer controller (Synchronous Data Tr)
transfer controller (SDTC) 28
It has.

In the main storage device 21, data to be processed is arranged in units of pages having a predetermined structure (for example, pages # 1 to #n are stored).
In the TSDT 27, the correspondence between the offset address (transfer source) in the main memory page and the PFR 24 is defined. That is, the TSDT 27 is the source (source)
ce) column and destination (destination)
ON) column, offset addresses (transfer sources) are sequentially arranged in the source column, and destinations (output port numbers) are arranged in the destination column corresponding to the offset addresses.

The PAR 24 stores a page number designating a page to be processed in the main storage device 21. This page number is updated by the processor 22 as described later. The page number stored in the PAR 24 is given to the address generation circuit 28a. On the other hand, the PCTR 25 repeats count start and reset at a predetermined cycle (for example, processing time allocated to each page) in response to a start reset signal from an external device (not shown). Now, when the start signal is given to the PCTR 25, the PC
TR25 starts counting and sends a count signal to TSDT.
Give to 27. The offset address and the output port number are read from the TSDT 27 according to the count signal. Specifically, assuming that the PCTR 25 sequentially outputs the first to N-th count signals, the first offset address from the TSDT 27 and the first offset address corresponding to the first offset address are transmitted in accordance with the first count signal. The output port number is read. When receiving the N-th count signal, the N-th offset address and the N-th offset address corresponding to the N-th offset address are received from the TSDT 27.
Is read out. These first to Nth
Are sequentially given to the address generation circuit 28a, and the first to N-th output port numbers are sequentially given to the switch control circuit 28b.

As described above, the page number is given to the address generation circuit 28a, whereby the address generation circuit 28a knows the page to be accessed, that is, the page to be prefetched. Then, the address generation circuit 28a
Generates a main storage address according to the page number and the first to N-th offset addresses, and reads out data of the designated page. Now, assuming that the page number is # 0,
The data of page # 0 is read according to the main storage address (that is, the first to N-th offset addresses), read as first to N-th # 0 data, and supplied to the switch circuit 28c.

As described above, the switch control circuit 28b is provided with the first to Nth output port numbers, and the switch control circuit 28b has the switch circuit 28c according to the first to Nth output port numbers. To control. For example, when receiving the first output port number, the switch control circuit 28b controls the switch circuit 28c to supply the first # 0 data to the first PFR 26. Similarly, when receiving the N-th output port number, the switch control circuit 28b controls the switch circuit 28c to supply the N-th # 0 data to the first PFR 26. As a result, the first to Nth PFR
26 stores the first through N-th # 0 data, respectively. That is, it is prefetched.

In the processor 22, the first to N-th PFs
Processing (data processing) is performed using the prefetched data in R26, and when this data processing is completed, the next necessary data is stored according to the program (application program) running on the processor 22. The page number is set in PAR24. That is, the page number stored in the PAR 24 is updated. At this time, PCTR2
5 is reset by the external device and starts counting again. That is, the PCTR 25 is reset when counting to the N-th count.

As described above, the data transfer from the main storage device 21 to the prefetch register 26 is performed by the synchronous data transfer controller 28, and when the processing cycle of one page ends, the PAR 24 is updated according to the application program. Will be. Then, the same prefetch is repeated again for the changed designated page.

As is apparent from the above description, a page on the main storage device 21 to be processed during the page processing period is designated by PAR2, and may be referred to in the internal processing of data in the page to be processed. Since the data and the transfer destination are specified by the TSDT 27, if the TSDT 27 is defined in advance according to the application program, the data to be transferred can be minimized, and as a result, the effective prefetch It can be performed.

Therefore, in the case of an application program in which the data structure in each page and the processing for each page are fixed, not only can the hit rate in prefetch be increased, but also the storage space for storing the prefetched data (ie, The number of prefetch registers) can be small, and a high-speed register can be used as a prefetch space.

In addition, in the above-described embodiment, since the source operand required by the processor exists in a predetermined register at a predetermined time, it is not necessary to describe complicated memory addressing in the program body. Moreover, since the TSDT and the program itself are highly independent,
Both changes are easy.

As a result, the above-described prefetch device performs processing for executing fixed processing at high speed at a constant period, for example,
Ideal for communication processing.

[0025]

As described above, according to the present invention, a page to be processed and data to be prefetched in the page to be processed are explicitly specified, and the data is specified in synchronization with the processing cycle of each page. Since the data is fetched to (register), the prefetch hit rate is high. Moreover, since the source operand required by the processor exists in a predetermined register at a predetermined time,
Another advantage is that the source operand specification description in the program body is simplified.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating an embodiment of a prefetch control device according to the present invention.

FIG. 2 is a diagram for explaining conventional prefetch control.

[Explanation of symbols]

21 Main Storage 22 Processor 23 Prefetch Controller 24 Page Address Register (PAR) 25 Page Counter (PCTR) 26 Prefetch Register (PFR) 27 Time-Source-Destination Table (T
SDT) 28 Synchronous data transfer controller (SDTC)

Claims (5)

[Claims] 1. A prefetch control device disposed between a main storage device in which data to be processed is stored in units of pages and a processor that processes the data to be processed, for prefetching the data to be processed, A storage unit for storing the data to be processed as prefetch data, a table in which an address in the page and a transfer destination corresponding to the address in the page are defined, and a page processing cycle when the page to be processed is specified. Control means for reading out the data in the page to be processed as the data to be processed based on the address in the page, and prefetching the data to be processed in the area in the storage device designated by the transfer destination. Prefetch control device. 2. The prefetch control device according to claim 1, wherein said storage means is a plurality of registers.
A prefetch control device, wherein each of the plurality of registers is the area. 3. The prefetch control device according to claim 2, wherein a page address register that specifies the page to be processed, and a page that executes a count during the page processing period and sends out a count signal representing a count number. A prefetch control device comprising: a counter; and wherein the in-page address and the transfer destination are read out from the table in synchronization with the count signal. 4. The prefetch control device according to claim 3, wherein the control unit accesses the main storage device in accordance with the page to be processed and the address in the page to store the data in the page to be processed. A prefetch control device comprising: an access unit that reads out data to be processed; and a transfer unit that transfers the data to be processed to the prefetch register specified by the transfer destination. 5. The prefetch control device according to claim 1, wherein the control means controls the transfer of the data to be processed in synchronization with the address in the page and the transfer destination. Prefetch control device.